socfpga_common.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  4. */
  5. #ifndef __CONFIG_SOCFPGA_COMMON_H__
  6. #define __CONFIG_SOCFPGA_COMMON_H__
  7. #include <linux/stringify.h>
  8. /*
  9. * High level configuration
  10. */
  11. #define CONFIG_CLOCKS
  12. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  13. /*
  14. * Memory configurations
  15. */
  16. #define PHYS_SDRAM_1 0x0
  17. #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
  18. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  19. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
  20. #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
  21. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  22. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  23. /* SPL memory allocation configuration, this is for FAT implementation */
  24. #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
  25. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
  26. #endif
  27. #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
  28. CONFIG_SYS_SPL_MALLOC_SIZE)
  29. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
  30. CONFIG_SYS_INIT_RAM_SIZE)
  31. #endif
  32. /*
  33. * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  34. * SRAM as bootcounter storage. Make sure to not put the stack directly
  35. * at this address to not overwrite the bootcounter by checking, if the
  36. * bootcounter address is located in the internal SRAM.
  37. */
  38. #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
  39. (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
  40. CONFIG_SYS_INIT_RAM_SIZE)))
  41. #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
  42. #else
  43. #define CONFIG_SPL_STACK \
  44. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  45. #endif
  46. /*
  47. * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  48. * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  49. * in U-Boot pre-reloc is higher than in SPL.
  50. */
  51. #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
  52. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
  53. #else
  54. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
  55. #endif
  56. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  57. /*
  58. * U-Boot general configurations
  59. */
  60. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  61. /* Print buffer size */
  62. #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  63. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  64. /* Boot argument buffer size */
  65. /*
  66. * Cache
  67. */
  68. #define CONFIG_SYS_L2_PL310
  69. #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
  70. /*
  71. * Ethernet on SoC (EMAC)
  72. */
  73. #ifdef CONFIG_CMD_NET
  74. #define CONFIG_DW_ALTDESCRIPTOR
  75. #endif
  76. /*
  77. * FPGA Driver
  78. */
  79. #ifdef CONFIG_CMD_FPGA
  80. #define CONFIG_FPGA_COUNT 1
  81. #endif
  82. /*
  83. * L4 OSC1 Timer 0
  84. */
  85. #ifndef CONFIG_TIMER
  86. #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
  87. #define CONFIG_SYS_TIMER_COUNTS_DOWN
  88. #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
  89. #ifndef CONFIG_SYS_TIMER_RATE
  90. #define CONFIG_SYS_TIMER_RATE 25000000
  91. #endif
  92. #endif
  93. /*
  94. * L4 Watchdog
  95. */
  96. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  97. #define CONFIG_DW_WDT_CLOCK_KHZ 25000
  98. /*
  99. * MMC Driver
  100. */
  101. #ifdef CONFIG_CMD_MMC
  102. /* FIXME */
  103. /* using smaller max blk cnt to avoid flooding the limited stack we have */
  104. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
  105. #endif
  106. /*
  107. * NAND Support
  108. */
  109. #ifdef CONFIG_NAND_DENALI
  110. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  111. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  112. #define CONFIG_SYS_NAND_ONFI_DETECTION
  113. #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
  114. #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
  115. #endif
  116. /*
  117. * QSPI support
  118. */
  119. /* QSPI reference clock */
  120. #ifndef __ASSEMBLY__
  121. unsigned int cm_get_qspi_controller_clk_hz(void);
  122. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  123. #endif
  124. /*
  125. * USB
  126. */
  127. /*
  128. * USB Gadget (DFU, UMS)
  129. */
  130. #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
  131. #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
  132. #define DFU_DEFAULT_POLL_TIMEOUT 300
  133. /* USB IDs */
  134. #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
  135. #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
  136. #endif
  137. /*
  138. * U-Boot environment
  139. */
  140. /* Environment for SDMMC boot */
  141. /* Environment for QSPI boot */
  142. /*
  143. * SPL
  144. *
  145. * SRAM Memory layout for gen 5:
  146. *
  147. * 0xFFFF_0000 ...... Start of SRAM
  148. * 0xFFFF_xxxx ...... Top of stack (grows down)
  149. * 0xFFFF_yyyy ...... Global Data
  150. * 0xFFFF_zzzz ...... Malloc area
  151. * 0xFFFF_FFFF ...... End of SRAM
  152. *
  153. * SRAM Memory layout for Arria 10:
  154. * 0xFFE0_0000 ...... Start of SRAM (bottom)
  155. * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
  156. * 0xFFEy_yyyy ...... Global Data
  157. * 0xFFEz_zzzz ...... Malloc area (grows up to top)
  158. * 0xFFE3_FFFF ...... End of SRAM (top)
  159. */
  160. #ifndef CONFIG_SPL_TEXT_BASE
  161. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  162. #endif
  163. /* SPL SDMMC boot support */
  164. #ifdef CONFIG_SPL_MMC_SUPPORT
  165. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  166. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  167. #endif
  168. #else
  169. #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
  170. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
  171. #endif
  172. #endif
  173. /* SPL QSPI boot support */
  174. /* SPL NAND boot support */
  175. #ifdef CONFIG_SPL_NAND_SUPPORT
  176. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  177. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  178. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  179. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
  180. #endif
  181. #endif
  182. /* Extra Environment */
  183. #ifndef CONFIG_SPL_BUILD
  184. #ifdef CONFIG_CMD_DHCP
  185. #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
  186. #else
  187. #define BOOT_TARGET_DEVICES_DHCP(func)
  188. #endif
  189. #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
  190. #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
  191. #else
  192. #define BOOT_TARGET_DEVICES_PXE(func)
  193. #endif
  194. #ifdef CONFIG_CMD_MMC
  195. #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
  196. #else
  197. #define BOOT_TARGET_DEVICES_MMC(func)
  198. #endif
  199. #define BOOT_TARGET_DEVICES(func) \
  200. BOOT_TARGET_DEVICES_MMC(func) \
  201. BOOT_TARGET_DEVICES_PXE(func) \
  202. BOOT_TARGET_DEVICES_DHCP(func)
  203. #include <config_distro_bootcmd.h>
  204. #ifndef CONFIG_EXTRA_ENV_SETTINGS
  205. #define CONFIG_EXTRA_ENV_SETTINGS \
  206. "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  207. "bootm_size=0xa000000\0" \
  208. "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
  209. "fdt_addr_r=0x02000000\0" \
  210. "scriptaddr=0x02100000\0" \
  211. "pxefile_addr_r=0x02200000\0" \
  212. "ramdisk_addr_r=0x02300000\0" \
  213. "socfpga_legacy_reset_compat=1\0" \
  214. BOOTENV
  215. #endif
  216. #endif
  217. #endif /* __CONFIG_SOCFPGA_COMMON_H__ */