sbc8349.h 9.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * WindRiver SBC8349 U-Boot configuration file.
  4. * Copyright (c) 2006, 2007 Wind River Systems, Inc.
  5. *
  6. * Paul Gortmaker <paul.gortmaker@windriver.com>
  7. * Based on the MPC8349EMDS config.
  8. */
  9. /*
  10. * sbc8349 board configuration file.
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_E300 1 /* E300 Family */
  18. /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  19. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  20. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  21. /*
  22. * DDR Setup
  23. */
  24. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  25. #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  26. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  27. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
  28. /*
  29. * 32-bit data path mode.
  30. *
  31. * Please note that using this mode for devices with the real density of 64-bit
  32. * effectively reduces the amount of available memory due to the effect of
  33. * wrapping around while translating address to row/columns, for example in the
  34. * 256MB module the upper 128MB get aliased with contents of the lower
  35. * 128MB); normally this define should be used for devices with real 32-bit
  36. * data path.
  37. */
  38. #undef CONFIG_DDR_32BIT
  39. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  40. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
  41. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  42. #define CONFIG_DDR_2T_TIMING
  43. #if defined(CONFIG_SPD_EEPROM)
  44. /*
  45. * Determine DDR configuration from I2C interface.
  46. */
  47. #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
  48. #else
  49. /*
  50. * Manually set up DDR parameters
  51. * NB: manual DDR setup untested on sbc834x
  52. */
  53. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  54. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  55. | CSCONFIG_ROW_BIT_13 \
  56. | CSCONFIG_COL_BIT_10)
  57. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  58. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  59. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  60. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  61. #if defined(CONFIG_DDR_32BIT)
  62. /* set burst length to 8 for 32-bit data path */
  63. /* DLL,normal,seq,4/2.5, 8 burst len */
  64. #define CONFIG_SYS_DDR_MODE 0x00000023
  65. #else
  66. /* the default burst length is 4 - for 64-bit data path */
  67. /* DLL,normal,seq,4/2.5, 4 burst len */
  68. #define CONFIG_SYS_DDR_MODE 0x00000022
  69. #endif
  70. #endif
  71. /*
  72. * SDRAM on the Local Bus
  73. */
  74. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  75. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  76. /*
  77. * FLASH on the Local Bus
  78. */
  79. #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
  80. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  81. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  82. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  83. #undef CONFIG_SYS_FLASH_CHECKSUM
  84. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  85. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  86. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  87. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  88. #define CONFIG_SYS_RAMBOOT
  89. #else
  90. #undef CONFIG_SYS_RAMBOOT
  91. #endif
  92. #define CONFIG_SYS_INIT_RAM_LOCK 1
  93. /* Initial RAM address */
  94. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  95. /* Size of used area in RAM*/
  96. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  97. #define CONFIG_SYS_GBL_DATA_OFFSET \
  98. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  99. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  100. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  101. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  102. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  103. /*
  104. * Serial Port
  105. */
  106. #define CONFIG_SYS_NS16550_SERIAL
  107. #define CONFIG_SYS_NS16550_REG_SIZE 1
  108. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  109. #define CONFIG_SYS_BAUDRATE_TABLE \
  110. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  111. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  112. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  113. /* I2C */
  114. #define CONFIG_SYS_I2C
  115. #define CONFIG_SYS_I2C_FSL
  116. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  117. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  118. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  119. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  120. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  121. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  122. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
  123. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  124. /* TSEC */
  125. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  126. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  127. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  128. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  129. /*
  130. * General PCI
  131. * Addresses are mapped 1-1.
  132. */
  133. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  134. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  135. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  136. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  137. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  138. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  139. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  140. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  141. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  142. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  143. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  144. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  145. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  146. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  147. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  148. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  149. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  150. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  151. #if defined(CONFIG_PCI)
  152. #if !defined(CONFIG_PCI_PNP)
  153. #define PCI_ENET0_IOADDR 0xFIXME
  154. #define PCI_ENET0_MEMADDR 0xFIXME
  155. #define PCI_IDSEL_NUMBER 0xFIXME
  156. #endif
  157. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  158. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  159. #endif /* CONFIG_PCI */
  160. /*
  161. * TSEC configuration
  162. */
  163. #if defined(CONFIG_TSEC_ENET)
  164. #define CONFIG_TSEC1 1
  165. #define CONFIG_TSEC1_NAME "TSEC0"
  166. #define CONFIG_TSEC2 1
  167. #define CONFIG_TSEC2_NAME "TSEC1"
  168. #define CONFIG_PHY_BCM5421S 1
  169. #define TSEC1_PHY_ADDR 0x19
  170. #define TSEC2_PHY_ADDR 0x1a
  171. #define TSEC1_PHYIDX 0
  172. #define TSEC2_PHYIDX 0
  173. #define TSEC1_FLAGS TSEC_GIGABIT
  174. #define TSEC2_FLAGS TSEC_GIGABIT
  175. /* Options are: TSEC[0-1] */
  176. #define CONFIG_ETHPRIME "TSEC0"
  177. #endif /* CONFIG_TSEC_ENET */
  178. /*
  179. * Environment
  180. */
  181. #ifndef CONFIG_SYS_RAMBOOT
  182. /* Address and size of Redundant Environment Sector */
  183. #endif
  184. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  185. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  186. /*
  187. * BOOTP options
  188. */
  189. #define CONFIG_BOOTP_BOOTFILESIZE
  190. #undef CONFIG_WATCHDOG /* watchdog disabled */
  191. /*
  192. * Miscellaneous configurable options
  193. */
  194. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  195. /*
  196. * For booting Linux, the board info and command line data
  197. * have to be in the first 256 MB of memory, since this is
  198. * the maximum mapped by the Linux kernel during initialization.
  199. */
  200. /* Initial Memory map for Linux*/
  201. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  202. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  203. /* System IO Config */
  204. #define CONFIG_SYS_SICRH 0
  205. #define CONFIG_SYS_SICRL SICRL_LDP_A
  206. #ifdef CONFIG_PCI
  207. #define CONFIG_PCI_INDIRECT_BRIDGE
  208. #endif
  209. #if defined(CONFIG_CMD_KGDB)
  210. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  211. #endif
  212. /*
  213. * Environment Configuration
  214. */
  215. #if defined(CONFIG_TSEC_ENET)
  216. #define CONFIG_HAS_ETH0
  217. #define CONFIG_HAS_ETH1
  218. #endif
  219. #define CONFIG_HOSTNAME "SBC8349"
  220. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  221. #define CONFIG_BOOTFILE "uImage"
  222. /* default location for tftp and bootm */
  223. #define CONFIG_LOADADDR 800000
  224. #define CONFIG_EXTRA_ENV_SETTINGS \
  225. "netdev=eth0\0" \
  226. "hostname=sbc8349\0" \
  227. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  228. "nfsroot=${serverip}:${rootpath}\0" \
  229. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  230. "addip=setenv bootargs ${bootargs} " \
  231. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  232. ":${hostname}:${netdev}:off panic=1\0" \
  233. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  234. "flash_nfs=run nfsargs addip addtty;" \
  235. "bootm ${kernel_addr}\0" \
  236. "flash_self=run ramargs addip addtty;" \
  237. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  238. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  239. "bootm\0" \
  240. "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
  241. "update=protect off ff800000 ff83ffff; " \
  242. "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
  243. "upd=run load update\0" \
  244. "fdtaddr=780000\0" \
  245. "fdtfile=sbc8349.dtb\0" \
  246. ""
  247. #define CONFIG_NFSBOOTCOMMAND \
  248. "setenv bootargs root=/dev/nfs rw " \
  249. "nfsroot=$serverip:$rootpath " \
  250. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  251. "$netdev:off " \
  252. "console=$consoledev,$baudrate $othbootargs;" \
  253. "tftp $loadaddr $bootfile;" \
  254. "tftp $fdtaddr $fdtfile;" \
  255. "bootm $loadaddr - $fdtaddr"
  256. #define CONFIG_RAMBOOTCOMMAND \
  257. "setenv bootargs root=/dev/ram rw " \
  258. "console=$consoledev,$baudrate $othbootargs;" \
  259. "tftp $ramdiskaddr $ramdiskfile;" \
  260. "tftp $loadaddr $bootfile;" \
  261. "tftp $fdtaddr $fdtfile;" \
  262. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  263. #define CONFIG_BOOTCOMMAND "run flash_self"
  264. #endif /* __CONFIG_H */