px30_common.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef __CONFIG_PX30_COMMON_H
  6. #define __CONFIG_PX30_COMMON_H
  7. #include "rockchip-common.h"
  8. #define CONFIG_SYS_CBSIZE 1024
  9. #define CONFIG_SKIP_LOWLEVEL_INIT
  10. #define CONFIG_SYS_NS16550_MEM32
  11. #define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
  12. #define COUNTER_FREQUENCY 24000000
  13. /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
  14. #define CONFIG_IRAM_BASE 0xff020000
  15. #define CONFIG_SYS_INIT_SP_ADDR 0x00400000
  16. #define CONFIG_SYS_LOAD_ADDR 0x00800800
  17. #define CONFIG_SPL_STACK 0x00400000
  18. #define CONFIG_SPL_MAX_SIZE 0x20000
  19. #define CONFIG_SPL_BSS_START_ADDR 0x4000000
  20. #define CONFIG_SPL_BSS_MAX_SIZE 0x4000
  21. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
  22. #define GICD_BASE 0xff131000
  23. #define GICC_BASE 0xff132000
  24. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
  25. #define CONFIG_SYS_SDRAM_BASE 0
  26. #define SDRAM_MAX_SIZE 0xff000000
  27. #define SDRAM_BANK_SIZE (2UL << 30)
  28. #ifndef CONFIG_SPL_BUILD
  29. #define ENV_MEM_LAYOUT_SETTINGS \
  30. "scriptaddr=0x00500000\0" \
  31. "pxefile_addr_r=0x00600000\0" \
  32. "fdt_addr_r=0x08300000\0" \
  33. "kernel_addr_r=0x00280000\0" \
  34. "kernel_addr_c=0x03e80000\0" \
  35. "ramdisk_addr_r=0x0a200000\0"
  36. #include <config_distro_bootcmd.h>
  37. #define CONFIG_EXTRA_ENV_SETTINGS \
  38. ENV_MEM_LAYOUT_SETTINGS \
  39. "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  40. "partitions=" PARTS_DEFAULT \
  41. ROCKCHIP_DEVICE_SETTINGS \
  42. BOOTENV
  43. #endif
  44. #endif