p1_p2_rdb_pc.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * QorIQ RDB boards configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #if defined(CONFIG_TARGET_P1020RDB_PC)
  13. #define CONFIG_BOARDNAME "P1020RDB-PC"
  14. #define CONFIG_NAND_FSL_ELBC
  15. #define CONFIG_VSC7385_ENET
  16. #define CONFIG_SLIC
  17. #define __SW_BOOT_MASK 0x03
  18. #define __SW_BOOT_NOR 0x5c
  19. #define __SW_BOOT_SPI 0x1c
  20. #define __SW_BOOT_SD 0x9c
  21. #define __SW_BOOT_NAND 0xec
  22. #define __SW_BOOT_PCIE 0x6c
  23. #define CONFIG_SYS_L2_SIZE (256 << 10)
  24. #endif
  25. /*
  26. * P1020RDB-PD board has user selectable switches for evaluating different
  27. * frequency and boot options for the P1020 device. The table that
  28. * follow describe the available options. The front six binary number was in
  29. * accordance with SW3[1:6].
  30. * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  31. * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  32. * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  33. * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  34. * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  35. * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  36. * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  37. */
  38. #if defined(CONFIG_TARGET_P1020RDB_PD)
  39. #define CONFIG_BOARDNAME "P1020RDB-PD"
  40. #define CONFIG_NAND_FSL_ELBC
  41. #define CONFIG_VSC7385_ENET
  42. #define CONFIG_SLIC
  43. #define __SW_BOOT_MASK 0x03
  44. #define __SW_BOOT_NOR 0x64
  45. #define __SW_BOOT_SPI 0x34
  46. #define __SW_BOOT_SD 0x24
  47. #define __SW_BOOT_NAND 0x44
  48. #define __SW_BOOT_PCIE 0x74
  49. #define CONFIG_SYS_L2_SIZE (256 << 10)
  50. /*
  51. * Dynamic MTD Partition support with mtdparts
  52. */
  53. #endif
  54. #if defined(CONFIG_TARGET_P2020RDB)
  55. #define CONFIG_BOARDNAME "P2020RDB-PC"
  56. #define CONFIG_NAND_FSL_ELBC
  57. #define CONFIG_VSC7385_ENET
  58. #define __SW_BOOT_MASK 0x03
  59. #define __SW_BOOT_NOR 0xc8
  60. #define __SW_BOOT_SPI 0x28
  61. #define __SW_BOOT_SD 0x68 /* or 0x18 */
  62. #define __SW_BOOT_NAND 0xe8
  63. #define __SW_BOOT_PCIE 0xa8
  64. #define CONFIG_SYS_L2_SIZE (512 << 10)
  65. /*
  66. * Dynamic MTD Partition support with mtdparts
  67. */
  68. #endif
  69. #ifdef CONFIG_SDCARD
  70. #define CONFIG_SPL_FLUSH_IMAGE
  71. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  72. #define CONFIG_SPL_PAD_TO 0x20000
  73. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  74. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  75. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  76. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  77. #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
  78. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  79. #ifdef CONFIG_SPL_BUILD
  80. #define CONFIG_SPL_COMMON_INIT_DDR
  81. #endif
  82. #endif
  83. #ifdef CONFIG_SPIFLASH
  84. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  85. #define CONFIG_SPL_FLUSH_IMAGE
  86. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  87. #define CONFIG_SPL_PAD_TO 0x20000
  88. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  89. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  90. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  91. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  92. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  93. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  94. #ifdef CONFIG_SPL_BUILD
  95. #define CONFIG_SPL_COMMON_INIT_DDR
  96. #endif
  97. #endif
  98. #ifdef CONFIG_MTD_RAW_NAND
  99. #ifdef CONFIG_TPL_BUILD
  100. #define CONFIG_SPL_FLUSH_IMAGE
  101. #define CONFIG_SPL_NAND_INIT
  102. #define CONFIG_SPL_COMMON_INIT_DDR
  103. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  104. #define CONFIG_TPL_TEXT_BASE 0xf8f81000
  105. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  106. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  107. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  108. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  109. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  110. #elif defined(CONFIG_SPL_BUILD)
  111. #define CONFIG_SPL_INIT_MINIMAL
  112. #define CONFIG_SPL_FLUSH_IMAGE
  113. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  114. #define CONFIG_SPL_MAX_SIZE 4096
  115. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  116. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  117. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  118. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  119. #endif /* not CONFIG_TPL_BUILD */
  120. #define CONFIG_SPL_PAD_TO 0x20000
  121. #define CONFIG_TPL_PAD_TO 0x20000
  122. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  123. #endif
  124. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  125. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  126. #endif
  127. #ifndef CONFIG_SYS_MONITOR_BASE
  128. #ifdef CONFIG_TPL_BUILD
  129. #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
  130. #elif defined(CONFIG_SPL_BUILD)
  131. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  132. #else
  133. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  134. #endif
  135. #endif
  136. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  137. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  138. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  139. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  140. #define CONFIG_LBA48
  141. #if defined(CONFIG_TARGET_P2020RDB)
  142. #define CONFIG_SYS_CLK_FREQ 100000000
  143. #else
  144. #define CONFIG_SYS_CLK_FREQ 66666666
  145. #endif
  146. #define CONFIG_DDR_CLK_FREQ 66666666
  147. #define CONFIG_HWCONFIG
  148. /*
  149. * These can be toggled for performance analysis, otherwise use default.
  150. */
  151. #define CONFIG_L2_CACHE
  152. #define CONFIG_BTB
  153. #define CONFIG_ENABLE_36BIT_PHYS
  154. #define CONFIG_SYS_CCSRBAR 0xffe00000
  155. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  156. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  157. SPL code*/
  158. #ifdef CONFIG_SPL_BUILD
  159. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  160. #endif
  161. /* DDR Setup */
  162. #define CONFIG_SYS_DDR_RAW_TIMING
  163. #define CONFIG_DDR_SPD
  164. #define CONFIG_SYS_SPD_BUS_NUM 1
  165. #define SPD_EEPROM_ADDRESS 0x52
  166. #if defined(CONFIG_TARGET_P1020RDB_PD)
  167. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
  168. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  169. #else
  170. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
  171. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  172. #endif
  173. #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  174. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  175. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  176. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  177. /* Default settings for DDR3 */
  178. #ifndef CONFIG_TARGET_P2020RDB
  179. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  180. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  181. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  182. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  183. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  184. #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  185. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  186. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  187. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  188. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  189. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  190. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  191. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  192. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  193. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  194. #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  195. #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  196. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  197. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  198. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  199. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  200. #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  201. #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  202. #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  203. #define CONFIG_SYS_DDR_MODE_1 0x40461520
  204. #define CONFIG_SYS_DDR_MODE_2 0x8000c000
  205. #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  206. #endif
  207. /*
  208. * Memory map
  209. *
  210. * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  211. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
  212. * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  213. * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
  214. * (early boot only)
  215. * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
  216. * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
  217. * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
  218. * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
  219. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  220. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  221. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  222. */
  223. /*
  224. * Local Bus Definitions
  225. */
  226. #if defined(CONFIG_TARGET_P1020RDB_PD)
  227. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  228. #define CONFIG_SYS_FLASH_BASE 0xec000000
  229. #else
  230. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
  231. #define CONFIG_SYS_FLASH_BASE 0xef000000
  232. #endif
  233. #ifdef CONFIG_PHYS_64BIT
  234. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  235. #else
  236. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  237. #endif
  238. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  239. | BR_PS_16 | BR_V)
  240. #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  241. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  242. #define CONFIG_SYS_FLASH_QUIET_TEST
  243. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  244. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  245. #undef CONFIG_SYS_FLASH_CHECKSUM
  246. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  247. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  248. #define CONFIG_SYS_FLASH_EMPTY_INFO
  249. /* Nand Flash */
  250. #ifdef CONFIG_NAND_FSL_ELBC
  251. #define CONFIG_SYS_NAND_BASE 0xff800000
  252. #ifdef CONFIG_PHYS_64BIT
  253. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  254. #else
  255. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  256. #endif
  257. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  258. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  259. #if defined(CONFIG_TARGET_P1020RDB_PD)
  260. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  261. #else
  262. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  263. #endif
  264. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  265. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  266. | BR_PS_8 /* Port Size = 8 bit */ \
  267. | BR_MS_FCM /* MSEL = FCM */ \
  268. | BR_V) /* valid */
  269. #if defined(CONFIG_TARGET_P1020RDB_PD)
  270. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
  271. | OR_FCM_PGS /* Large Page*/ \
  272. | OR_FCM_CSCT \
  273. | OR_FCM_CST \
  274. | OR_FCM_CHT \
  275. | OR_FCM_SCY_1 \
  276. | OR_FCM_TRLX \
  277. | OR_FCM_EHTR)
  278. #else
  279. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
  280. | OR_FCM_CSCT \
  281. | OR_FCM_CST \
  282. | OR_FCM_CHT \
  283. | OR_FCM_SCY_1 \
  284. | OR_FCM_TRLX \
  285. | OR_FCM_EHTR)
  286. #endif
  287. #endif /* CONFIG_NAND_FSL_ELBC */
  288. #define CONFIG_SYS_INIT_RAM_LOCK
  289. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  290. #ifdef CONFIG_PHYS_64BIT
  291. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  292. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  293. /* The assembler doesn't like typecast */
  294. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  295. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  296. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  297. #else
  298. /* Initial L1 address */
  299. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  300. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  301. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  302. #endif
  303. /* Size of used area in RAM */
  304. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  305. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  306. GENERATED_GBL_DATA_SIZE)
  307. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  308. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  309. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  310. #define CONFIG_SYS_CPLD_BASE 0xffa00000
  311. #ifdef CONFIG_PHYS_64BIT
  312. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
  313. #else
  314. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  315. #endif
  316. /* CPLD config size: 1Mb */
  317. #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
  318. BR_PS_8 | BR_V)
  319. #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
  320. #define CONFIG_SYS_PMC_BASE 0xff980000
  321. #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  322. #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  323. BR_PS_8 | BR_V)
  324. #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  325. OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  326. OR_GPCM_EAD)
  327. #ifdef CONFIG_MTD_RAW_NAND
  328. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  329. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  330. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  331. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  332. #else
  333. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  334. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  335. #ifdef CONFIG_NAND_FSL_ELBC
  336. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  337. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  338. #endif
  339. #endif
  340. #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
  341. #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
  342. /* Vsc7385 switch */
  343. #ifdef CONFIG_VSC7385_ENET
  344. #define __VSCFW_ADDR "vscfw_addr=ef000000"
  345. #define CONFIG_SYS_VSC7385_BASE 0xffb00000
  346. #ifdef CONFIG_PHYS_64BIT
  347. #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
  348. #else
  349. #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
  350. #endif
  351. #define CONFIG_SYS_VSC7385_BR_PRELIM \
  352. (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
  353. #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
  354. OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
  355. OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
  356. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
  357. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
  358. /* The size of the VSC7385 firmware image */
  359. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  360. #endif
  361. /*
  362. * Config the L2 Cache as L2 SRAM
  363. */
  364. #if defined(CONFIG_SPL_BUILD)
  365. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  366. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  367. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  368. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  369. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  370. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  371. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  372. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  373. #if defined(CONFIG_TARGET_P2020RDB)
  374. #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
  375. #else
  376. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  377. #endif
  378. #elif defined(CONFIG_MTD_RAW_NAND)
  379. #ifdef CONFIG_TPL_BUILD
  380. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  381. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  382. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  383. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  384. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  385. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  386. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  387. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  388. #else
  389. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  390. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  391. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  392. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  393. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  394. #endif /* CONFIG_TPL_BUILD */
  395. #endif
  396. #endif
  397. /* Serial Port - controlled on board with jumper J8
  398. * open - index 2
  399. * shorted - index 1
  400. */
  401. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  402. #define CONFIG_SYS_NS16550_SERIAL
  403. #define CONFIG_SYS_NS16550_REG_SIZE 1
  404. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  405. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  406. #define CONFIG_NS16550_MIN_FUNCTIONS
  407. #endif
  408. #define CONFIG_SYS_BAUDRATE_TABLE \
  409. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  410. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  411. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  412. /* I2C */
  413. #ifndef CONFIG_DM_I2C
  414. #define CONFIG_SYS_I2C
  415. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  416. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  417. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  418. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  419. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  420. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  421. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  422. #else
  423. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  424. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  425. #endif
  426. #define CONFIG_SYS_I2C_FSL
  427. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  428. #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  429. /*
  430. * I2C2 EEPROM
  431. */
  432. #undef CONFIG_ID_EEPROM
  433. #define CONFIG_RTC_PT7C4338
  434. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  435. #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  436. /* enable read and write access to EEPROM */
  437. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  438. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  439. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  440. #if defined(CONFIG_PCI)
  441. /*
  442. * General PCI
  443. * Memory space is mapped 1-1, but I/O space must start from 0.
  444. */
  445. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  446. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  447. #ifdef CONFIG_PHYS_64BIT
  448. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  449. #else
  450. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  451. #endif
  452. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  453. #ifdef CONFIG_PHYS_64BIT
  454. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  455. #else
  456. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  457. #endif
  458. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  459. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  460. #ifdef CONFIG_PHYS_64BIT
  461. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  462. #else
  463. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  464. #endif
  465. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  466. #ifdef CONFIG_PHYS_64BIT
  467. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  468. #else
  469. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  470. #endif
  471. #if !defined(CONFIG_DM_PCI)
  472. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  473. #define CONFIG_PCI_INDIRECT_BRIDGE
  474. #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
  475. #ifdef CONFIG_PHYS_64BIT
  476. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  477. #else
  478. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  479. #endif
  480. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  481. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  482. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  483. #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
  484. #ifdef CONFIG_PHYS_64BIT
  485. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  486. #else
  487. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  488. #endif
  489. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  490. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  491. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  492. #endif
  493. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  494. #endif /* CONFIG_PCI */
  495. #if defined(CONFIG_TSEC_ENET)
  496. #define CONFIG_TSEC1
  497. #define CONFIG_TSEC1_NAME "eTSEC1"
  498. #define CONFIG_TSEC2
  499. #define CONFIG_TSEC2_NAME "eTSEC2"
  500. #define CONFIG_TSEC3
  501. #define CONFIG_TSEC3_NAME "eTSEC3"
  502. #define TSEC1_PHY_ADDR 2
  503. #define TSEC2_PHY_ADDR 0
  504. #define TSEC3_PHY_ADDR 1
  505. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  506. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  507. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  508. #define TSEC1_PHYIDX 0
  509. #define TSEC2_PHYIDX 0
  510. #define TSEC3_PHYIDX 0
  511. #define CONFIG_ETHPRIME "eTSEC1"
  512. #define CONFIG_HAS_ETH0
  513. #define CONFIG_HAS_ETH1
  514. #define CONFIG_HAS_ETH2
  515. #endif /* CONFIG_TSEC_ENET */
  516. #ifdef CONFIG_QE
  517. /* QE microcode/firmware address */
  518. #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
  519. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  520. #endif /* CONFIG_QE */
  521. /*
  522. * Environment
  523. */
  524. #if defined(CONFIG_SDCARD)
  525. #define CONFIG_FSL_FIXED_MMC_LOCATION
  526. #elif defined(CONFIG_MTD_RAW_NAND)
  527. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  528. #ifdef CONFIG_TPL_BUILD
  529. #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  530. #endif
  531. #elif defined(CONFIG_SYS_RAMBOOT)
  532. #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  533. #endif
  534. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  535. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  536. /*
  537. * USB
  538. */
  539. #define CONFIG_HAS_FSL_DR_USB
  540. #if defined(CONFIG_HAS_FSL_DR_USB)
  541. #ifdef CONFIG_USB_EHCI_HCD
  542. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  543. #define CONFIG_USB_EHCI_FSL
  544. #endif
  545. #endif
  546. #if defined(CONFIG_TARGET_P1020RDB_PD)
  547. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  548. #endif
  549. #ifdef CONFIG_MMC
  550. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  551. #endif
  552. #undef CONFIG_WATCHDOG /* watchdog disabled */
  553. /*
  554. * Miscellaneous configurable options
  555. */
  556. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  557. /*
  558. * For booting Linux, the board info and command line data
  559. * have to be in the first 64 MB of memory, since this is
  560. * the maximum mapped by the Linux kernel during initialization.
  561. */
  562. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  563. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  564. #if defined(CONFIG_CMD_KGDB)
  565. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  566. #endif
  567. /*
  568. * Environment Configuration
  569. */
  570. #define CONFIG_HOSTNAME "unknown"
  571. #define CONFIG_ROOTPATH "/opt/nfsroot"
  572. #define CONFIG_BOOTFILE "uImage"
  573. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  574. /* default location for tftp and bootm */
  575. #define CONFIG_LOADADDR 1000000
  576. #ifdef __SW_BOOT_NOR
  577. #define __NOR_RST_CMD \
  578. norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
  579. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  580. #endif
  581. #ifdef __SW_BOOT_SPI
  582. #define __SPI_RST_CMD \
  583. spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
  584. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  585. #endif
  586. #ifdef __SW_BOOT_SD
  587. #define __SD_RST_CMD \
  588. sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
  589. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  590. #endif
  591. #ifdef __SW_BOOT_NAND
  592. #define __NAND_RST_CMD \
  593. nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
  594. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  595. #endif
  596. #ifdef __SW_BOOT_PCIE
  597. #define __PCIE_RST_CMD \
  598. pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
  599. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  600. #endif
  601. #define CONFIG_EXTRA_ENV_SETTINGS \
  602. "netdev=eth0\0" \
  603. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  604. "loadaddr=1000000\0" \
  605. "bootfile=uImage\0" \
  606. "tftpflash=tftpboot $loadaddr $uboot; " \
  607. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  608. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  609. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  610. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  611. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  612. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
  613. "consoledev=ttyS0\0" \
  614. "ramdiskaddr=2000000\0" \
  615. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  616. "fdtaddr=1e00000\0" \
  617. "bdev=sda1\0" \
  618. "jffs2nor=mtdblock3\0" \
  619. "norbootaddr=ef080000\0" \
  620. "norfdtaddr=ef040000\0" \
  621. "jffs2nand=mtdblock9\0" \
  622. "nandbootaddr=100000\0" \
  623. "nandfdtaddr=80000\0" \
  624. "ramdisk_size=120000\0" \
  625. "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
  626. "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
  627. __stringify(__VSCFW_ADDR)"\0" \
  628. __stringify(__NOR_RST_CMD)"\0" \
  629. __stringify(__SPI_RST_CMD)"\0" \
  630. __stringify(__SD_RST_CMD)"\0" \
  631. __stringify(__NAND_RST_CMD)"\0" \
  632. __stringify(__PCIE_RST_CMD)"\0"
  633. #define CONFIG_NFSBOOTCOMMAND \
  634. "setenv bootargs root=/dev/nfs rw " \
  635. "nfsroot=$serverip:$rootpath " \
  636. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  637. "console=$consoledev,$baudrate $othbootargs;" \
  638. "tftp $loadaddr $bootfile;" \
  639. "tftp $fdtaddr $fdtfile;" \
  640. "bootm $loadaddr - $fdtaddr"
  641. #define CONFIG_HDBOOT \
  642. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  643. "console=$consoledev,$baudrate $othbootargs;" \
  644. "usb start;" \
  645. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  646. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  647. "bootm $loadaddr - $fdtaddr"
  648. #define CONFIG_USB_FAT_BOOT \
  649. "setenv bootargs root=/dev/ram rw " \
  650. "console=$consoledev,$baudrate $othbootargs " \
  651. "ramdisk_size=$ramdisk_size;" \
  652. "usb start;" \
  653. "fatload usb 0:2 $loadaddr $bootfile;" \
  654. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  655. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  656. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  657. #define CONFIG_USB_EXT2_BOOT \
  658. "setenv bootargs root=/dev/ram rw " \
  659. "console=$consoledev,$baudrate $othbootargs " \
  660. "ramdisk_size=$ramdisk_size;" \
  661. "usb start;" \
  662. "ext2load usb 0:4 $loadaddr $bootfile;" \
  663. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  664. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  665. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  666. #define CONFIG_NORBOOT \
  667. "setenv bootargs root=/dev/$jffs2nor rw " \
  668. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  669. "bootm $norbootaddr - $norfdtaddr"
  670. #define CONFIG_RAMBOOTCOMMAND \
  671. "setenv bootargs root=/dev/ram rw " \
  672. "console=$consoledev,$baudrate $othbootargs " \
  673. "ramdisk_size=$ramdisk_size;" \
  674. "tftp $ramdiskaddr $ramdiskfile;" \
  675. "tftp $loadaddr $bootfile;" \
  676. "tftp $fdtaddr $fdtfile;" \
  677. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  678. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  679. #endif /* __CONFIG_H */