mpc8308_p1m.h 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  5. *
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <linux/stringify.h>
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1 /* E300 family */
  14. /*
  15. * On-board devices
  16. *
  17. * TSECs
  18. */
  19. #define CONFIG_TSEC1
  20. #define CONFIG_TSEC2
  21. #define CONFIG_SYS_GPIO1_PRELIM
  22. /* GPIO Default input/output settings */
  23. #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
  24. /*
  25. * Default GPIO values:
  26. * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
  27. */
  28. #define CONFIG_SYS_GPIO1_DAT 0x08008C00
  29. /*
  30. * SERDES
  31. */
  32. #define CONFIG_FSL_SERDES
  33. #define CONFIG_FSL_SERDES1 0xe3000
  34. /*
  35. * DDR Setup
  36. */
  37. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  38. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  39. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  40. | DDRCDR_PZ_LOZ \
  41. | DDRCDR_NZ_LOZ \
  42. | DDRCDR_ODT \
  43. | DDRCDR_Q_DRN)
  44. /* 0x7b880001 */
  45. /*
  46. * Manually set up DDR parameters
  47. * consist of two chips HY5PS12621BFP-C4 from HYNIX
  48. */
  49. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  50. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  51. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  52. | CSCONFIG_ODT_RD_NEVER \
  53. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  54. | CSCONFIG_ROW_BIT_13 \
  55. | CSCONFIG_COL_BIT_10)
  56. /* 0x80010102 */
  57. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  58. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  59. | (0 << TIMING_CFG0_WRT_SHIFT) \
  60. | (0 << TIMING_CFG0_RRT_SHIFT) \
  61. | (0 << TIMING_CFG0_WWT_SHIFT) \
  62. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  63. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  64. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  65. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  66. /* 0x00220802 */
  67. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  68. | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  69. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  70. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  71. | (6 << TIMING_CFG1_REFREC_SHIFT) \
  72. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  73. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  74. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  75. /* 0x27256222 */
  76. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  77. | (4 << TIMING_CFG2_CPO_SHIFT) \
  78. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  79. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  80. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  81. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  82. | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  83. /* 0x121048c5 */
  84. #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  85. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  86. /* 0x03600100 */
  87. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  88. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  89. | SDRAM_CFG_DBW_32)
  90. /* 0x43080000 */
  91. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  92. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  93. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  94. /* ODT 150ohm CL=3, AL=1 on SDRAM */
  95. #define CONFIG_SYS_DDR_MODE2 0x00000000
  96. /*
  97. * Memory test
  98. */
  99. /*
  100. * The reserved memory
  101. */
  102. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  103. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  104. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  105. /*
  106. * Initial RAM Base Address Setup
  107. */
  108. #define CONFIG_SYS_INIT_RAM_LOCK 1
  109. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  110. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  111. #define CONFIG_SYS_GBL_DATA_OFFSET \
  112. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  113. /*
  114. * FLASH on the Local Bus
  115. */
  116. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  117. #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
  118. #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
  119. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  120. #define CONFIG_SYS_MAX_FLASH_SECT 512
  121. /* Flash Erase Timeout (ms) */
  122. #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
  123. /* Flash Write Timeout (ms) */
  124. #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
  125. /*
  126. * SJA1000 CAN controller on Local Bus
  127. */
  128. #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
  129. /*
  130. * CPLD on Local Bus
  131. */
  132. #define CONFIG_SYS_CPLD_BASE 0xFBFF8000
  133. /*
  134. * Serial Port
  135. */
  136. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  137. #define CONFIG_SYS_NS16550_SERIAL
  138. #define CONFIG_SYS_NS16550_REG_SIZE 1
  139. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  140. #define CONFIG_SYS_BAUDRATE_TABLE \
  141. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  142. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  143. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  144. /* I2C */
  145. #define CONFIG_SYS_I2C
  146. #define CONFIG_SYS_I2C_FSL
  147. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  148. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  149. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  150. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  151. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  152. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  153. /*
  154. * General PCI
  155. * Addresses are mapped 1-1.
  156. */
  157. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  158. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  159. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  160. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  161. #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  162. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  163. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  164. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  165. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  166. /* enable PCIE clock */
  167. #define CONFIG_SYS_SCCR_PCIEXP1CM 1
  168. #define CONFIG_PCI_INDIRECT_BRIDGE
  169. #define CONFIG_PCIE
  170. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  171. #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
  172. /*
  173. * TSEC
  174. */
  175. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  176. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  177. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  178. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  179. /*
  180. * TSEC ethernet configuration
  181. */
  182. #define CONFIG_TSEC1_NAME "eTSEC0"
  183. #define CONFIG_TSEC2_NAME "eTSEC1"
  184. #define TSEC1_PHY_ADDR 1
  185. #define TSEC2_PHY_ADDR 2
  186. #define TSEC1_PHYIDX 0
  187. #define TSEC2_PHYIDX 0
  188. #define TSEC1_FLAGS 0
  189. #define TSEC2_FLAGS 0
  190. /* Options are: eTSEC[0-1] */
  191. #define CONFIG_ETHPRIME "eTSEC0"
  192. /*
  193. * Environment
  194. */
  195. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  196. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  197. /*
  198. * BOOTP options
  199. */
  200. #define CONFIG_BOOTP_BOOTFILESIZE
  201. /*
  202. * Miscellaneous configurable options
  203. */
  204. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  205. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  206. /* Boot Argument Buffer Size */
  207. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  208. /*
  209. * For booting Linux, the board info and command line data
  210. * have to be in the first 8 MB of memory, since this is
  211. * the maximum mapped by the Linux kernel during initialization.
  212. */
  213. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  214. /*
  215. * Environment Configuration
  216. */
  217. #if defined(CONFIG_TSEC_ENET)
  218. #define CONFIG_HAS_ETH0
  219. #define CONFIG_HAS_ETH1
  220. #endif
  221. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  222. #define CONFIG_EXTRA_ENV_SETTINGS \
  223. "netdev=eth0\0" \
  224. "consoledev=ttyS0\0" \
  225. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  226. "nfsroot=${serverip}:${rootpath}\0" \
  227. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  228. "addip=setenv bootargs ${bootargs} " \
  229. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  230. ":${hostname}:${netdev}:off panic=1\0" \
  231. "addtty=setenv bootargs ${bootargs}" \
  232. " console=${consoledev},${baudrate}\0" \
  233. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  234. "addmisc=setenv bootargs ${bootargs}\0" \
  235. "kernel_addr=FC0A0000\0" \
  236. "fdt_addr=FC2A0000\0" \
  237. "ramdisk_addr=FC2C0000\0" \
  238. "u-boot=mpc8308_p1m/u-boot.bin\0" \
  239. "kernel_addr_r=1000000\0" \
  240. "fdt_addr_r=C00000\0" \
  241. "hostname=mpc8308_p1m\0" \
  242. "bootfile=mpc8308_p1m/uImage\0" \
  243. "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
  244. "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
  245. "flash_self=run ramargs addip addtty addmtd addmisc;" \
  246. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  247. "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
  248. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  249. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  250. "tftp ${fdt_addr_r} ${fdtfile};" \
  251. "run nfsargs addip addtty addmtd addmisc;" \
  252. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  253. "bootcmd=run flash_self\0" \
  254. "load=tftp ${loadaddr} ${u-boot}\0" \
  255. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  256. " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  257. " +${filesize};cp.b ${fileaddr} " \
  258. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  259. "upd=run load update\0" \
  260. #endif /* __CONFIG_H */