lx2160a_common.h 9.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018-2020 NXP
  4. */
  5. #ifndef __LX2_COMMON_H
  6. #define __LX2_COMMON_H
  7. #include <asm/arch/stream_id_lsch3.h>
  8. #include <asm/arch/config.h>
  9. #include <asm/arch/soc.h>
  10. #define CONFIG_REMAKE_ELF
  11. #define CONFIG_FSL_LAYERSCAPE
  12. #define CONFIG_GICV3
  13. #define CONFIG_FSL_TZPC_BP147
  14. #define CONFIG_FSL_MEMAC
  15. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  16. #define CONFIG_SYS_FLASH_BASE 0x20000000
  17. #define CONFIG_SKIP_LOWLEVEL_INIT
  18. /* DDR */
  19. #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  20. #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
  21. #define CONFIG_VERY_BIG_RAM
  22. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  23. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  24. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
  25. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
  26. #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
  27. #define CONFIG_DDR_SPD
  28. #define CONFIG_DDR_ECC
  29. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  30. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  31. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  32. #define SPD_EEPROM_ADDRESS1 0x51
  33. #define SPD_EEPROM_ADDRESS2 0x52
  34. #define SPD_EEPROM_ADDRESS3 0x53
  35. #define SPD_EEPROM_ADDRESS4 0x54
  36. #define SPD_EEPROM_ADDRESS5 0x55
  37. #define SPD_EEPROM_ADDRESS6 0x56
  38. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  39. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  40. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  41. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  42. #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
  43. #define CONFIG_SYS_MONITOR_LEN (936 * 1024)
  44. /* Miscellaneous configurable options */
  45. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  46. /* SMP Definitinos */
  47. #define CPU_RELEASE_ADDR secondary_boot_addr
  48. /* Generic Timer Definitions */
  49. /*
  50. * This is not an accurate number. It is used in start.S. The frequency
  51. * will be udpated later when get_bus_freq(0) is available.
  52. */
  53. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  54. /* Size of malloc() pool */
  55. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  56. /* Serial Port */
  57. #define CONFIG_PL01X_SERIAL
  58. #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
  59. #define CONFIG_SYS_SERIAL0 0x21c0000
  60. #define CONFIG_SYS_SERIAL1 0x21d0000
  61. #define CONFIG_SYS_SERIAL2 0x21e0000
  62. #define CONFIG_SYS_SERIAL3 0x21f0000
  63. /*below might needs to be removed*/
  64. #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
  65. (void *)CONFIG_SYS_SERIAL1, \
  66. (void *)CONFIG_SYS_SERIAL2, \
  67. (void *)CONFIG_SYS_SERIAL3 }
  68. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  69. /* MC firmware */
  70. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  71. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  72. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  73. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  74. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  75. /* Define phy_reset function to boot the MC based on mcinitcmd.
  76. * This happens late enough to properly fixup u-boot env MAC addresses.
  77. */
  78. #define CONFIG_RESET_PHY_R
  79. /*
  80. * Carve out a DDR region which will not be used by u-boot/Linux
  81. *
  82. * It will be used by MC and Debug Server. The MC region must be
  83. * 512MB aligned, so the min size to hide is 512MB.
  84. */
  85. #ifdef CONFIG_FSL_MC_ENET
  86. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
  87. #endif
  88. /* I2C bus multiplexer */
  89. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  90. #define I2C_MUX_CH_DEFAULT 0x8
  91. /* RTC */
  92. #define RTC
  93. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  94. /* EEPROM */
  95. #define CONFIG_ID_EEPROM
  96. #define CONFIG_SYS_I2C_EEPROM_NXID
  97. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  98. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  99. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  100. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  101. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  102. /* Qixis */
  103. #define CONFIG_FSL_QIXIS
  104. #define CONFIG_QIXIS_I2C_ACCESS
  105. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  106. /* PCI */
  107. #ifdef CONFIG_PCI
  108. #define CONFIG_SYS_PCI_64BIT
  109. #define CONFIG_PCI_SCAN_SHOW
  110. #endif
  111. /* MMC */
  112. #ifdef CONFIG_MMC
  113. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  114. #endif
  115. /* SATA */
  116. #ifdef CONFIG_SCSI
  117. #define CONFIG_SCSI_AHCI_PLAT
  118. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  119. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  120. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  121. #define CONFIG_SYS_SCSI_MAX_LUN 1
  122. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  123. CONFIG_SYS_SCSI_MAX_LUN)
  124. #endif
  125. /* USB */
  126. #ifdef CONFIG_USB
  127. #define CONFIG_HAS_FSL_XHCI_USB
  128. #ifndef CONFIG_TARGET_LX2162AQDS
  129. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  130. #endif
  131. #endif
  132. /* FlexSPI */
  133. #ifdef CONFIG_NXP_FSPI
  134. #define NXP_FSPI_FLASH_SIZE SZ_64M
  135. #define NXP_FSPI_FLASH_NUM 1
  136. #endif
  137. #ifndef __ASSEMBLY__
  138. unsigned long get_board_sys_clk(void);
  139. unsigned long get_board_ddr_clk(void);
  140. #endif
  141. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  142. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  143. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
  144. #define CONFIG_HWCONFIG
  145. #define HWCONFIG_BUFFER_SIZE 128
  146. /* Monitor Command Prompt */
  147. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  148. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  149. sizeof(CONFIG_SYS_PROMPT) + 16)
  150. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  151. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  152. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  153. /* Initial environment variables */
  154. #define XSPI_MC_INIT_CMD \
  155. "sf probe 0:0 && " \
  156. "sf read 0x80640000 0x640000 0x80000 && " \
  157. "env exists secureboot && " \
  158. "esbc_validate 0x80640000 && " \
  159. "esbc_validate 0x80680000; " \
  160. "sf read 0x80a00000 0xa00000 0x300000 && " \
  161. "sf read 0x80e00000 0xe00000 0x100000; " \
  162. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  163. #define SD_MC_INIT_CMD \
  164. "mmc read 0x80a00000 0x5000 0x1200;" \
  165. "mmc read 0x80e00000 0x7000 0x800;" \
  166. "env exists secureboot && " \
  167. "mmc read 0x80640000 0x3200 0x20 && " \
  168. "mmc read 0x80680000 0x3400 0x20 && " \
  169. "esbc_validate 0x80640000 && " \
  170. "esbc_validate 0x80680000 ;" \
  171. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  172. #define SD2_MC_INIT_CMD \
  173. "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
  174. "mmc read 0x80e00000 0x7000 0x800;" \
  175. "env exists secureboot && " \
  176. "mmc read 0x80640000 0x3200 0x20 && " \
  177. "mmc read 0x80680000 0x3400 0x20 && " \
  178. "esbc_validate 0x80640000 && " \
  179. "esbc_validate 0x80680000 ;" \
  180. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  181. #define EXTRA_ENV_SETTINGS \
  182. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  183. "ramdisk_addr=0x800000\0" \
  184. "ramdisk_size=0x2000000\0" \
  185. "fdt_high=0xa0000000\0" \
  186. "initrd_high=0xffffffffffffffff\0" \
  187. "fdt_addr=0x64f00000\0" \
  188. "kernel_start=0x1000000\0" \
  189. "kernelheader_start=0x600000\0" \
  190. "scriptaddr=0x80000000\0" \
  191. "scripthdraddr=0x80080000\0" \
  192. "fdtheader_addr_r=0x80100000\0" \
  193. "kernelheader_addr_r=0x80200000\0" \
  194. "kernel_addr_r=0x81000000\0" \
  195. "kernelheader_size=0x40000\0" \
  196. "fdt_addr_r=0x90000000\0" \
  197. "load_addr=0xa0000000\0" \
  198. "kernel_size=0x2800000\0" \
  199. "kernel_addr_sd=0x8000\0" \
  200. "kernelhdr_addr_sd=0x3000\0" \
  201. "kernel_size_sd=0x14000\0" \
  202. "kernelhdr_size_sd=0x20\0" \
  203. "console=ttyAMA0,38400n8\0" \
  204. BOOTENV \
  205. "mcmemsize=0x70000000\0" \
  206. XSPI_MC_INIT_CMD \
  207. "scan_dev_for_boot_part=" \
  208. "part list ${devtype} ${devnum} devplist; " \
  209. "env exists devplist || setenv devplist 1; " \
  210. "for distro_bootpart in ${devplist}; do " \
  211. "if fstype ${devtype} " \
  212. "${devnum}:${distro_bootpart} " \
  213. "bootfstype; then " \
  214. "run scan_dev_for_boot; " \
  215. "fi; " \
  216. "done\0" \
  217. "boot_a_script=" \
  218. "load ${devtype} ${devnum}:${distro_bootpart} " \
  219. "${scriptaddr} ${prefix}${script}; " \
  220. "env exists secureboot && load ${devtype} " \
  221. "${devnum}:${distro_bootpart} " \
  222. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  223. "&& esbc_validate ${scripthdraddr};" \
  224. "source ${scriptaddr}\0"
  225. #define XSPI_NOR_BOOTCOMMAND \
  226. "sf probe 0:0; " \
  227. "sf read 0x806c0000 0x6c0000 0x40000; " \
  228. "env exists mcinitcmd && env exists secureboot" \
  229. " && esbc_validate 0x806c0000; " \
  230. "sf read 0x80d00000 0xd00000 0x100000; " \
  231. "env exists mcinitcmd && " \
  232. "fsl_mc lazyapply dpl 0x80d00000; " \
  233. "run distro_bootcmd;run xspi_bootcmd; " \
  234. "env exists secureboot && esbc_halt;"
  235. #define SD_BOOTCOMMAND \
  236. "env exists mcinitcmd && mmcinfo; " \
  237. "mmc read 0x80d00000 0x6800 0x800; " \
  238. "env exists mcinitcmd && env exists secureboot " \
  239. " && mmc read 0x806C0000 0x3600 0x20 " \
  240. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  241. "&& fsl_mc lazyapply dpl 0x80d00000;" \
  242. "run distro_bootcmd;run sd_bootcmd;" \
  243. "env exists secureboot && esbc_halt;"
  244. #define SD2_BOOTCOMMAND \
  245. "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
  246. "mmc read 0x80d00000 0x6800 0x800; " \
  247. "env exists mcinitcmd && env exists secureboot " \
  248. " && mmc read 0x806C0000 0x3600 0x20 " \
  249. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  250. "&& fsl_mc lazyapply dpl 0x80d00000;" \
  251. "run distro_bootcmd;run sd2_bootcmd;" \
  252. "env exists secureboot && esbc_halt;"
  253. #define BOOT_TARGET_DEVICES(func) \
  254. func(USB, usb, 0) \
  255. func(MMC, mmc, 0) \
  256. func(MMC, mmc, 1) \
  257. func(SCSI, scsi, 0) \
  258. func(DHCP, dhcp, na)
  259. #include <config_distro_bootcmd.h>
  260. #endif /* __LX2_COMMON_H */