ls2080aqds.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017, 2019-2020 NXP
  4. * Copyright 2015 Freescale Semiconductor
  5. */
  6. #ifndef __LS2_QDS_H
  7. #define __LS2_QDS_H
  8. #include "ls2080a_common.h"
  9. #ifndef __ASSEMBLY__
  10. unsigned long get_board_sys_clk(void);
  11. unsigned long get_board_ddr_clk(void);
  12. #endif
  13. #ifdef CONFIG_FSL_QSPI
  14. #define CONFIG_QIXIS_I2C_ACCESS
  15. #ifndef CONFIG_DM_I2C
  16. #define CONFIG_SYS_I2C_EARLY_INIT
  17. #endif
  18. #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
  19. #endif
  20. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  21. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  22. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  23. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
  24. #define CONFIG_DDR_SPD
  25. #define CONFIG_DDR_ECC
  26. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  27. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  28. #define SPD_EEPROM_ADDRESS1 0x51
  29. #define SPD_EEPROM_ADDRESS2 0x52
  30. #define SPD_EEPROM_ADDRESS3 0x53
  31. #define SPD_EEPROM_ADDRESS4 0x54
  32. #define SPD_EEPROM_ADDRESS5 0x55
  33. #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
  34. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  35. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  36. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  37. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  38. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  39. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  40. #endif
  41. /* SATA */
  42. #define CONFIG_SCSI_AHCI_PLAT
  43. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  44. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  45. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  46. #define CONFIG_SYS_SCSI_MAX_LUN 1
  47. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  48. CONFIG_SYS_SCSI_MAX_LUN)
  49. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  50. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  51. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  52. #define CONFIG_SYS_NOR0_CSPR \
  53. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  54. CSPR_PORT_SIZE_16 | \
  55. CSPR_MSEL_NOR | \
  56. CSPR_V)
  57. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  58. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  59. CSPR_PORT_SIZE_16 | \
  60. CSPR_MSEL_NOR | \
  61. CSPR_V)
  62. #define CONFIG_SYS_NOR1_CSPR \
  63. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
  64. CSPR_PORT_SIZE_16 | \
  65. CSPR_MSEL_NOR | \
  66. CSPR_V)
  67. #define CONFIG_SYS_NOR1_CSPR_EARLY \
  68. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  69. CSPR_PORT_SIZE_16 | \
  70. CSPR_MSEL_NOR | \
  71. CSPR_V)
  72. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  73. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  74. FTIM0_NOR_TEADC(0x5) | \
  75. FTIM0_NOR_TEAHC(0x5))
  76. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  77. FTIM1_NOR_TRAD_NOR(0x1a) |\
  78. FTIM1_NOR_TSEQRAD_NOR(0x13))
  79. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  80. FTIM2_NOR_TCH(0x4) | \
  81. FTIM2_NOR_TWPH(0x0E) | \
  82. FTIM2_NOR_TWP(0x1c))
  83. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  84. #define CONFIG_SYS_IFC_CCR 0x01000000
  85. #ifdef CONFIG_MTD_NOR_FLASH
  86. #define CONFIG_SYS_FLASH_QUIET_TEST
  87. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  88. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  89. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  90. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  91. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  92. #define CONFIG_SYS_FLASH_EMPTY_INFO
  93. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  94. CONFIG_SYS_FLASH_BASE + 0x40000000}
  95. #endif
  96. #define CONFIG_NAND_FSL_IFC
  97. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  98. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  99. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  100. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  101. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  102. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  103. | CSPR_V)
  104. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  105. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  106. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  107. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  108. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  109. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  110. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  111. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  112. #define CONFIG_SYS_NAND_ONFI_DETECTION
  113. /* ONFI NAND Flash mode0 Timing Params */
  114. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  115. FTIM0_NAND_TWP(0x18) | \
  116. FTIM0_NAND_TWCHT(0x07) | \
  117. FTIM0_NAND_TWH(0x0a))
  118. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  119. FTIM1_NAND_TWBE(0x39) | \
  120. FTIM1_NAND_TRR(0x0e) | \
  121. FTIM1_NAND_TRP(0x18))
  122. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  123. FTIM2_NAND_TREH(0x0a) | \
  124. FTIM2_NAND_TWHRE(0x1e))
  125. #define CONFIG_SYS_NAND_FTIM3 0x0
  126. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  127. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  128. #define CONFIG_MTD_NAND_VERIFY_WRITE
  129. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  130. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  131. #define QIXIS_LBMAP_SWITCH 0x06
  132. #define QIXIS_LBMAP_MASK 0x0f
  133. #define QIXIS_LBMAP_SHIFT 0
  134. #define QIXIS_LBMAP_DFLTBANK 0x00
  135. #define QIXIS_LBMAP_ALTBANK 0x04
  136. #define QIXIS_LBMAP_NAND 0x09
  137. #define QIXIS_LBMAP_SD 0x00
  138. #define QIXIS_LBMAP_QSPI 0x0f
  139. #define QIXIS_RST_CTL_RESET 0x31
  140. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  141. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  142. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  143. #define QIXIS_RCW_SRC_NAND 0x107
  144. #define QIXIS_RCW_SRC_SD 0x40
  145. #define QIXIS_RCW_SRC_QSPI 0x62
  146. #define QIXIS_RST_FORCE_MEM 0x01
  147. #define CONFIG_SYS_CSPR3_EXT (0x0)
  148. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  149. | CSPR_PORT_SIZE_8 \
  150. | CSPR_MSEL_GPCM \
  151. | CSPR_V)
  152. #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  153. | CSPR_PORT_SIZE_8 \
  154. | CSPR_MSEL_GPCM \
  155. | CSPR_V)
  156. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  157. #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
  158. /* QIXIS Timing parameters for IFC CS3 */
  159. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  160. FTIM0_GPCM_TEADC(0x0e) | \
  161. FTIM0_GPCM_TEAHC(0x0e))
  162. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  163. FTIM1_GPCM_TRAD(0x3f))
  164. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  165. FTIM2_GPCM_TCH(0xf) | \
  166. FTIM2_GPCM_TWP(0x3E))
  167. #define CONFIG_SYS_CS3_FTIM3 0x0
  168. #if defined(CONFIG_SPL)
  169. #if defined(CONFIG_NAND_BOOT)
  170. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  171. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
  172. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
  173. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  174. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  175. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  176. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  177. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  178. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  179. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  180. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
  181. #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
  182. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
  183. #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
  184. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  185. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  186. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  187. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  188. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  189. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  190. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  191. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  192. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  193. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  194. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  195. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  196. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  197. #define CONFIG_SPL_PAD_TO 0x20000
  198. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
  199. #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
  200. #endif
  201. #else
  202. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  203. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  204. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  205. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  206. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  207. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  208. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  209. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  210. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  211. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  212. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
  213. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
  214. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
  215. #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
  216. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  217. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  218. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  219. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  220. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  221. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  222. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  223. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  224. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  225. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  226. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  227. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  228. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  229. #endif
  230. /* Debug Server firmware */
  231. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  232. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
  233. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  234. /*
  235. * I2C
  236. */
  237. #define I2C_MUX_PCA_ADDR 0x77
  238. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  239. /* I2C bus multiplexer */
  240. #define I2C_MUX_CH_DEFAULT 0x8
  241. /* SPI */
  242. #ifdef CONFIG_FSL_DSPI
  243. #define CONFIG_SPI_FLASH_STMICRO
  244. #define CONFIG_SPI_FLASH_SST
  245. #define CONFIG_SPI_FLASH_EON
  246. #endif
  247. #ifdef CONFIG_FSL_QSPI
  248. #define CONFIG_SPI_FLASH_SPANSION
  249. #endif
  250. /*
  251. * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
  252. * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
  253. * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
  254. */
  255. #define FSL_QIXIS_BRDCFG9_QSPI 0x1
  256. /*
  257. * MMC
  258. */
  259. #ifdef CONFIG_MMC
  260. #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
  261. QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
  262. #endif
  263. /*
  264. * RTC configuration
  265. */
  266. #define RTC
  267. #define CONFIG_RTC_DS3231 1
  268. #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
  269. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  270. #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
  271. /* EEPROM */
  272. #define CONFIG_ID_EEPROM
  273. #define CONFIG_SYS_I2C_EEPROM_NXID
  274. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  275. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  276. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  277. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  278. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  279. #define CONFIG_FSL_MEMAC
  280. #ifdef CONFIG_PCI
  281. #define CONFIG_PCI_SCAN_SHOW
  282. #endif
  283. /* MMC */
  284. #ifdef CONFIG_MMC
  285. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  286. #endif
  287. /* Initial environment variables */
  288. #undef CONFIG_EXTRA_ENV_SETTINGS
  289. #ifdef CONFIG_NXP_ESBC
  290. #define CONFIG_EXTRA_ENV_SETTINGS \
  291. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  292. "loadaddr=0x80100000\0" \
  293. "kernel_addr=0x100000\0" \
  294. "ramdisk_addr=0x800000\0" \
  295. "ramdisk_size=0x2000000\0" \
  296. "fdt_high=0xa0000000\0" \
  297. "initrd_high=0xffffffffffffffff\0" \
  298. "kernel_start=0x581000000\0" \
  299. "kernel_load=0xa0000000\0" \
  300. "kernel_size=0x2800000\0" \
  301. "mcmemsize=0x40000000\0" \
  302. "mcinitcmd=esbc_validate 0x580640000;" \
  303. "esbc_validate 0x580680000;" \
  304. "fsl_mc start mc 0x580a00000" \
  305. " 0x580e00000 \0"
  306. #else
  307. #ifdef CONFIG_TFABOOT
  308. #define SD_MC_INIT_CMD \
  309. "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
  310. "mmc read 0x80e00000 0x7000 0x800;" \
  311. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  312. #define IFC_MC_INIT_CMD \
  313. "fsl_mc start mc 0x580a00000" \
  314. " 0x580e00000 \0"
  315. #define CONFIG_EXTRA_ENV_SETTINGS \
  316. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  317. "loadaddr=0x80100000\0" \
  318. "loadaddr_sd=0x90100000\0" \
  319. "kernel_addr=0x581000000\0" \
  320. "kernel_addr_sd=0x8000\0" \
  321. "ramdisk_addr=0x800000\0" \
  322. "ramdisk_size=0x2000000\0" \
  323. "fdt_high=0xa0000000\0" \
  324. "initrd_high=0xffffffffffffffff\0" \
  325. "kernel_start=0x581000000\0" \
  326. "kernel_start_sd=0x8000\0" \
  327. "kernel_load=0xa0000000\0" \
  328. "kernel_size=0x2800000\0" \
  329. "kernel_size_sd=0x14000\0" \
  330. "load_addr=0xa0000000\0" \
  331. "kernelheader_addr=0x580600000\0" \
  332. "kernelheader_addr_r=0x80200000\0" \
  333. "kernelheader_size=0x40000\0" \
  334. "BOARD=ls2088aqds\0" \
  335. "mcmemsize=0x70000000 \0" \
  336. "scriptaddr=0x80000000\0" \
  337. "scripthdraddr=0x80080000\0" \
  338. IFC_MC_INIT_CMD \
  339. BOOTENV \
  340. "boot_scripts=ls2088aqds_boot.scr\0" \
  341. "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
  342. "scan_dev_for_boot_part=" \
  343. "part list ${devtype} ${devnum} devplist; " \
  344. "env exists devplist || setenv devplist 1; " \
  345. "for distro_bootpart in ${devplist}; do " \
  346. "if fstype ${devtype} " \
  347. "${devnum}:${distro_bootpart} " \
  348. "bootfstype; then " \
  349. "run scan_dev_for_boot; " \
  350. "fi; " \
  351. "done\0" \
  352. "boot_a_script=" \
  353. "load ${devtype} ${devnum}:${distro_bootpart} " \
  354. "${scriptaddr} ${prefix}${script}; " \
  355. "env exists secureboot && load ${devtype} " \
  356. "${devnum}:${distro_bootpart} " \
  357. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  358. "&& esbc_validate ${scripthdraddr};" \
  359. "source ${scriptaddr}\0" \
  360. "nor_bootcmd=echo Trying load from nor..;" \
  361. "cp.b $kernel_addr $load_addr " \
  362. "$kernel_size ; env exists secureboot && " \
  363. "cp.b $kernelheader_addr $kernelheader_addr_r " \
  364. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  365. "bootm $load_addr#$BOARD\0" \
  366. "sd_bootcmd=echo Trying load from SD ..;" \
  367. "mmcinfo; mmc read $load_addr " \
  368. "$kernel_addr_sd $kernel_size_sd && " \
  369. "bootm $load_addr#$BOARD\0"
  370. #elif defined(CONFIG_SD_BOOT)
  371. #define CONFIG_EXTRA_ENV_SETTINGS \
  372. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  373. "loadaddr=0x90100000\0" \
  374. "kernel_addr=0x800\0" \
  375. "ramdisk_addr=0x800000\0" \
  376. "ramdisk_size=0x2000000\0" \
  377. "fdt_high=0xa0000000\0" \
  378. "initrd_high=0xffffffffffffffff\0" \
  379. "kernel_start=0x8000\0" \
  380. "kernel_load=0xa0000000\0" \
  381. "kernel_size=0x14000\0" \
  382. "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  383. "mmc read 0x80100000 0x7000 0x800;" \
  384. "fsl_mc start mc 0x80000000 0x80100000\0" \
  385. "mcmemsize=0x70000000 \0"
  386. #else
  387. #define CONFIG_EXTRA_ENV_SETTINGS \
  388. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  389. "loadaddr=0x80100000\0" \
  390. "kernel_addr=0x100000\0" \
  391. "ramdisk_addr=0x800000\0" \
  392. "ramdisk_size=0x2000000\0" \
  393. "fdt_high=0xa0000000\0" \
  394. "initrd_high=0xffffffffffffffff\0" \
  395. "kernel_start=0x581000000\0" \
  396. "kernel_load=0xa0000000\0" \
  397. "kernel_size=0x2800000\0" \
  398. "mcmemsize=0x40000000\0" \
  399. "mcinitcmd=fsl_mc start mc 0x580a00000" \
  400. " 0x580e00000 \0"
  401. #endif /* CONFIG_TFABOOT */
  402. #endif /* CONFIG_NXP_ESBC */
  403. #ifdef CONFIG_TFABOOT
  404. #define BOOT_TARGET_DEVICES(func) \
  405. func(USB, usb, 0) \
  406. func(MMC, mmc, 0) \
  407. func(SCSI, scsi, 0) \
  408. func(DHCP, dhcp, na)
  409. #include <config_distro_bootcmd.h>
  410. #define SD_BOOTCOMMAND \
  411. "env exists mcinitcmd && env exists secureboot "\
  412. "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
  413. "&& esbc_validate $load_addr; " \
  414. "env exists mcinitcmd && run mcinitcmd " \
  415. "&& mmc read 0x80d00000 0x6800 0x800 " \
  416. "&& fsl_mc lazyapply dpl 0x80d00000; " \
  417. "run distro_bootcmd;run sd_bootcmd; " \
  418. "env exists secureboot && esbc_halt;"
  419. #define IFC_NOR_BOOTCOMMAND \
  420. "env exists mcinitcmd && env exists secureboot "\
  421. "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
  422. "&& fsl_mc lazyapply dpl 0x580d00000;" \
  423. "run distro_bootcmd;run nor_bootcmd; " \
  424. "env exists secureboot && esbc_halt;"
  425. #endif
  426. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  427. #define CONFIG_FSL_MEMAC
  428. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  429. #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
  430. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  431. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  432. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  433. #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
  434. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  435. #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
  436. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  437. #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
  438. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  439. #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
  440. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  441. #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
  442. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  443. #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
  444. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  445. #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
  446. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  447. #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
  448. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  449. #endif
  450. #include <asm/fsl_secure_boot.h>
  451. #endif /* __LS2_QDS_H */