ls1088a_common.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #ifndef __LS1088_COMMON_H
  6. #define __LS1088_COMMON_H
  7. /* SPL build */
  8. #ifdef CONFIG_SPL_BUILD
  9. #define SPL_NO_BOARDINFO
  10. #define SPL_NO_QIXIS
  11. #define SPL_NO_PCI
  12. #define SPL_NO_ENV
  13. #define SPL_NO_RTC
  14. #define SPL_NO_USB
  15. #define SPL_NO_SATA
  16. #define SPL_NO_QSPI
  17. #define SPL_NO_IFC
  18. #undef CONFIG_DISPLAY_CPUINFO
  19. #endif
  20. #define CONFIG_REMAKE_ELF
  21. #include <asm/arch/stream_id_lsch3.h>
  22. #include <asm/arch/config.h>
  23. #include <asm/arch/soc.h>
  24. #define LS1088ARDB_PB_BOARD 0x4A
  25. /* Link Definitions */
  26. #ifdef CONFIG_TFABOOT
  27. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  28. #else
  29. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  30. #endif
  31. /* Link Definitions */
  32. #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
  33. #define CONFIG_SKIP_LOWLEVEL_INIT
  34. #define CONFIG_VERY_BIG_RAM
  35. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  36. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  37. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  38. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
  39. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
  40. /*
  41. * SMP Definitinos
  42. */
  43. #define CPU_RELEASE_ADDR secondary_boot_addr
  44. /* Size of malloc() pool */
  45. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  46. /* I2C */
  47. #ifndef CONFIG_DM_I2C
  48. #define CONFIG_SYS_I2C
  49. #endif
  50. /* Serial Port */
  51. #define CONFIG_SYS_NS16550_SERIAL
  52. #define CONFIG_SYS_NS16550_REG_SIZE 1
  53. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  54. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  55. #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
  56. /* IFC */
  57. #define CONFIG_FSL_IFC
  58. #endif
  59. /*
  60. * During booting, IFC is mapped at the region of 0x30000000.
  61. * But this region is limited to 256MB. To accommodate NOR, promjet
  62. * and FPGA. This region is divided as below:
  63. * 0x30000000 - 0x37ffffff : 128MB : NOR flash
  64. * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  65. * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  66. *
  67. * To accommodate bigger NOR flash and other devices, we will map IFC
  68. * chip selects to as below:
  69. * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  70. * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  71. * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  72. * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  73. * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  74. *
  75. * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  76. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  77. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  78. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  79. * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  80. */
  81. #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
  82. #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
  83. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  84. #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
  85. #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
  86. #ifndef __ASSEMBLY__
  87. unsigned long long get_qixis_addr(void);
  88. #endif
  89. #define QIXIS_BASE get_qixis_addr()
  90. #define QIXIS_BASE_PHYS 0x20000000
  91. #define QIXIS_BASE_PHYS_EARLY 0xC000000
  92. #define CONFIG_SYS_NAND_BASE 0x530000000ULL
  93. #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
  94. /* MC firmware */
  95. /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
  96. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  97. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  98. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  99. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  100. #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
  101. #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
  102. /* Define phy_reset function to boot the MC based on mcinitcmd.
  103. * This happens late enough to properly fixup u-boot env MAC addresses.
  104. */
  105. #define CONFIG_RESET_PHY_R
  106. /*
  107. * Carve out a DDR region which will not be used by u-boot/Linux
  108. *
  109. * It will be used by MC and Debug Server. The MC region must be
  110. * 512MB aligned, so the min size to hide is 512MB.
  111. */
  112. #if defined(CONFIG_FSL_MC_ENET)
  113. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
  114. #endif
  115. /* Miscellaneous configurable options */
  116. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  117. /* SATA */
  118. #ifdef CONFIG_SCSI
  119. #define CONFIG_SCSI_AHCI_PLAT
  120. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  121. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  122. #define CONFIG_SYS_SCSI_MAX_LUN 1
  123. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  124. CONFIG_SYS_SCSI_MAX_LUN)
  125. #endif
  126. /* Physical Memory Map */
  127. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  128. #define CONFIG_HWCONFIG
  129. #define HWCONFIG_BUFFER_SIZE 128
  130. /* #define CONFIG_DISPLAY_CPUINFO */
  131. #ifndef SPL_NO_ENV
  132. /* Initial environment variables */
  133. #define CONFIG_EXTRA_ENV_SETTINGS \
  134. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  135. "loadaddr=0x80100000\0" \
  136. "kernel_addr=0x100000\0" \
  137. "ramdisk_addr=0x800000\0" \
  138. "ramdisk_size=0x2000000\0" \
  139. "fdt_high=0xa0000000\0" \
  140. "initrd_high=0xffffffffffffffff\0" \
  141. "kernel_start=0x581000000\0" \
  142. "kernel_load=0xa0000000\0" \
  143. "kernel_size=0x2800000\0" \
  144. "console=ttyAMA0,38400n8\0" \
  145. "mcinitcmd=fsl_mc start mc 0x580a00000" \
  146. " 0x580e00000 \0"
  147. #ifndef CONFIG_TFABOOT
  148. #if defined(CONFIG_QSPI_BOOT)
  149. #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
  150. "sf read 0x80001000 0xd00000 0x100000;"\
  151. " fsl_mc lazyapply dpl 0x80001000 &&" \
  152. " sf read $kernel_load $kernel_start" \
  153. " $kernel_size && bootm $kernel_load"
  154. #elif defined(CONFIG_SD_BOOT)
  155. #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
  156. " fsl_mc lazyapply dpl 0x80001000 &&" \
  157. " mmc read $kernel_load $kernel_start" \
  158. " $kernel_size && bootm $kernel_load"
  159. #else /* NOR BOOT*/
  160. #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
  161. " cp.b $kernel_start $kernel_load" \
  162. " $kernel_size && bootm $kernel_load"
  163. #endif
  164. #endif /* CONFIG_TFABOOT */
  165. #endif
  166. /* Monitor Command Prompt */
  167. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  168. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  169. sizeof(CONFIG_SYS_PROMPT) + 16)
  170. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  171. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  172. #ifdef CONFIG_SPL
  173. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  174. #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
  175. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  176. #define CONFIG_SPL_MAX_SIZE 0x16000
  177. #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
  178. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  179. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
  180. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  181. #ifdef CONFIG_NXP_ESBC
  182. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  183. /*
  184. * HDR would be appended at end of image and copied to DDR along
  185. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  186. * size increases then increase this size in case of secure boot as
  187. * it uses raw u-boot image instead of fit image.
  188. */
  189. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  190. #else
  191. #define CONFIG_SYS_MONITOR_LEN 0x100000
  192. #endif /* ifdef CONFIG_NXP_ESBC */
  193. #endif
  194. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  195. #endif /* __LS1088_COMMON_H */