ls1043aqds.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __LS1043AQDS_H__
  6. #define __LS1043AQDS_H__
  7. #include "ls1043a_common.h"
  8. #ifndef __ASSEMBLY__
  9. unsigned long get_board_sys_clk(void);
  10. unsigned long get_board_ddr_clk(void);
  11. #endif
  12. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  13. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #define CONFIG_LAYERSCAPE_NS_ACCESS
  16. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  17. /* Physical Memory Map */
  18. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  19. #define CONFIG_DDR_SPD
  20. #define SPD_EEPROM_ADDRESS 0x51
  21. #define CONFIG_SYS_SPD_BUS_NUM 0
  22. #define CONFIG_DDR_ECC
  23. #ifdef CONFIG_DDR_ECC
  24. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  25. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  26. #endif
  27. #ifdef CONFIG_SYS_DPAA_FMAN
  28. #define RGMII_PHY1_ADDR 0x1
  29. #define RGMII_PHY2_ADDR 0x2
  30. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  31. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  32. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  33. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  34. /* PHY address on QSGMII riser card on slot 1 */
  35. #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  36. #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  37. #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  38. #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  39. /* PHY address on QSGMII riser card on slot 2 */
  40. #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  41. #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  42. #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  43. #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  44. #endif
  45. #ifdef CONFIG_RAMBOOT_PBL
  46. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
  47. #endif
  48. #ifdef CONFIG_NAND_BOOT
  49. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
  50. #endif
  51. #ifdef CONFIG_SD_BOOT
  52. #ifdef CONFIG_SD_BOOT_QSPI
  53. #define CONFIG_SYS_FSL_PBL_RCW \
  54. board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
  55. #else
  56. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
  57. #endif
  58. #endif
  59. /* LPUART */
  60. #ifdef CONFIG_LPUART
  61. #define CONFIG_LPUART_32B_REG
  62. #endif
  63. /* SATA */
  64. #define CONFIG_SCSI_AHCI_PLAT
  65. /* EEPROM */
  66. #define CONFIG_ID_EEPROM
  67. #define CONFIG_SYS_I2C_EEPROM_NXID
  68. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  69. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  70. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  71. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  72. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  73. #define CONFIG_SYS_SATA AHCI_BASE_ADDR
  74. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  75. #define CONFIG_SYS_SCSI_MAX_LUN 1
  76. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  77. CONFIG_SYS_SCSI_MAX_LUN)
  78. /*
  79. * IFC Definitions
  80. */
  81. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  82. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  83. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  84. CSPR_PORT_SIZE_16 | \
  85. CSPR_MSEL_NOR | \
  86. CSPR_V)
  87. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  88. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  89. + 0x8000000) | \
  90. CSPR_PORT_SIZE_16 | \
  91. CSPR_MSEL_NOR | \
  92. CSPR_V)
  93. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  94. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  95. CSOR_NOR_TRHZ_80)
  96. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  97. FTIM0_NOR_TEADC(0x5) | \
  98. FTIM0_NOR_TEAHC(0x5))
  99. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  100. FTIM1_NOR_TRAD_NOR(0x1a) | \
  101. FTIM1_NOR_TSEQRAD_NOR(0x13))
  102. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  103. FTIM2_NOR_TCH(0x4) | \
  104. FTIM2_NOR_TWPH(0xe) | \
  105. FTIM2_NOR_TWP(0x1c))
  106. #define CONFIG_SYS_NOR_FTIM3 0
  107. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  108. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  109. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  110. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  111. #define CONFIG_SYS_FLASH_EMPTY_INFO
  112. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  113. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  114. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  115. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  116. /*
  117. * NAND Flash Definitions
  118. */
  119. #define CONFIG_NAND_FSL_IFC
  120. #define CONFIG_SYS_NAND_BASE 0x7e800000
  121. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  122. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  123. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  124. | CSPR_PORT_SIZE_8 \
  125. | CSPR_MSEL_NAND \
  126. | CSPR_V)
  127. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  128. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  129. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  130. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  131. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  132. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  133. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  134. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  135. #define CONFIG_SYS_NAND_ONFI_DETECTION
  136. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  137. FTIM0_NAND_TWP(0x18) | \
  138. FTIM0_NAND_TWCHT(0x7) | \
  139. FTIM0_NAND_TWH(0xa))
  140. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  141. FTIM1_NAND_TWBE(0x39) | \
  142. FTIM1_NAND_TRR(0xe) | \
  143. FTIM1_NAND_TRP(0x18))
  144. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  145. FTIM2_NAND_TREH(0xa) | \
  146. FTIM2_NAND_TWHRE(0x1e))
  147. #define CONFIG_SYS_NAND_FTIM3 0x0
  148. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  149. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  150. #define CONFIG_MTD_NAND_VERIFY_WRITE
  151. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  152. #endif
  153. #ifdef CONFIG_NAND_BOOT
  154. #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
  155. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  156. #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
  157. #endif
  158. #if defined(CONFIG_TFABOOT) || \
  159. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  160. #define CONFIG_QIXIS_I2C_ACCESS
  161. #define CONFIG_SYS_I2C_EARLY_INIT
  162. #endif
  163. /*
  164. * QIXIS Definitions
  165. */
  166. #define CONFIG_FSL_QIXIS
  167. #ifdef CONFIG_FSL_QIXIS
  168. #define QIXIS_BASE 0x7fb00000
  169. #define QIXIS_BASE_PHYS QIXIS_BASE
  170. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  171. #define QIXIS_LBMAP_SWITCH 6
  172. #define QIXIS_LBMAP_MASK 0x0f
  173. #define QIXIS_LBMAP_SHIFT 0
  174. #define QIXIS_LBMAP_DFLTBANK 0x00
  175. #define QIXIS_LBMAP_ALTBANK 0x04
  176. #define QIXIS_LBMAP_NAND 0x09
  177. #define QIXIS_LBMAP_SD 0x00
  178. #define QIXIS_LBMAP_SD_QSPI 0xff
  179. #define QIXIS_LBMAP_QSPI 0xff
  180. #define QIXIS_RCW_SRC_NAND 0x106
  181. #define QIXIS_RCW_SRC_SD 0x040
  182. #define QIXIS_RCW_SRC_QSPI 0x045
  183. #define QIXIS_RST_CTL_RESET 0x41
  184. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  185. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  186. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  187. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  188. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  189. CSPR_PORT_SIZE_8 | \
  190. CSPR_MSEL_GPCM | \
  191. CSPR_V)
  192. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  193. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  194. CSOR_NOR_NOR_MODE_AVD_NOR | \
  195. CSOR_NOR_TRHZ_80)
  196. /*
  197. * QIXIS Timing parameters for IFC GPCM
  198. */
  199. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
  200. FTIM0_GPCM_TEADC(0x20) | \
  201. FTIM0_GPCM_TEAHC(0x10))
  202. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
  203. FTIM1_GPCM_TRAD(0x1f))
  204. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
  205. FTIM2_GPCM_TCH(0x8) | \
  206. FTIM2_GPCM_TWP(0xf0))
  207. #define CONFIG_SYS_FPGA_FTIM3 0x0
  208. #endif
  209. #ifdef CONFIG_TFABOOT
  210. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  211. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  212. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  213. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  214. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  215. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  216. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  217. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  218. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  219. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  220. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  221. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  222. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  223. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  224. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  225. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  226. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  227. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  228. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  229. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  230. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  231. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  232. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  233. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  234. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  235. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  236. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  237. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  238. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  239. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  240. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  241. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  242. #else
  243. #ifdef CONFIG_NAND_BOOT
  244. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  245. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  246. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  247. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  248. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  249. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  250. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  251. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  252. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  253. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  254. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  255. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  256. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  257. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  258. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  259. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  260. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  261. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  262. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  263. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  264. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  265. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  266. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  267. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  268. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  269. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  270. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  271. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  272. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  273. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  274. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  275. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  276. #else
  277. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  278. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  279. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  280. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  281. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  282. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  283. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  284. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  285. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  286. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  287. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  288. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  289. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  290. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  291. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  292. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  293. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  294. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  295. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  296. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  297. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  298. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  299. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  300. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  301. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  302. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  303. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  304. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  305. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  306. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  307. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  308. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  309. #endif
  310. #endif
  311. /*
  312. * I2C bus multiplexer
  313. */
  314. #define I2C_MUX_PCA_ADDR_PRI 0x77
  315. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  316. #define I2C_RETIMER_ADDR 0x18
  317. #define I2C_MUX_CH_DEFAULT 0x8
  318. #define I2C_MUX_CH_CH7301 0xC
  319. #define I2C_MUX_CH5 0xD
  320. #define I2C_MUX_CH7 0xF
  321. #define I2C_MUX_CH_VOL_MONITOR 0xa
  322. /* Voltage monitor on channel 2*/
  323. #define I2C_VOL_MONITOR_ADDR 0x40
  324. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  325. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  326. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  327. #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
  328. #ifndef CONFIG_SPL_BUILD
  329. #define CONFIG_VID
  330. #endif
  331. #define CONFIG_VOL_MONITOR_IR36021_SET
  332. #define CONFIG_VOL_MONITOR_INA220
  333. /* The lowest and highest voltage allowed for LS1043AQDS */
  334. #define VDD_MV_MIN 819
  335. #define VDD_MV_MAX 1212
  336. /*
  337. * Miscellaneous configurable options
  338. */
  339. #define CONFIG_SYS_HZ 1000
  340. #define CONFIG_SYS_INIT_SP_OFFSET \
  341. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  342. #ifdef CONFIG_SPL_BUILD
  343. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  344. #else
  345. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  346. #endif
  347. /*
  348. * Environment
  349. */
  350. #define CONFIG_CMDLINE_TAG
  351. #include <asm/fsl_secure_boot.h>
  352. #endif /* __LS1043AQDS_H__ */