ls1021aiot.h 5.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  9. #define CONFIG_SYS_FSL_CLK
  10. /*
  11. * Size of malloc() pool
  12. */
  13. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  14. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  15. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  16. #define CONFIG_SYS_CLK_FREQ 100000000
  17. #define CONFIG_DDR_CLK_FREQ 100000000
  18. /*
  19. * DDR: 800 MHz ( 1600 MT/s data rate )
  20. */
  21. #define DDR_SDRAM_CFG 0x470c0008
  22. #define DDR_CS0_BNDS 0x008000bf
  23. #define DDR_CS0_CONFIG 0x80014302
  24. #define DDR_TIMING_CFG_0 0x50550004
  25. #define DDR_TIMING_CFG_1 0xbcb38c56
  26. #define DDR_TIMING_CFG_2 0x0040d120
  27. #define DDR_TIMING_CFG_3 0x010e1000
  28. #define DDR_TIMING_CFG_4 0x00000001
  29. #define DDR_TIMING_CFG_5 0x03401400
  30. #define DDR_SDRAM_CFG_2 0x00401010
  31. #define DDR_SDRAM_MODE 0x00061c60
  32. #define DDR_SDRAM_MODE_2 0x00180000
  33. #define DDR_SDRAM_INTERVAL 0x18600618
  34. #define DDR_DDR_WRLVL_CNTL 0x8655f605
  35. #define DDR_DDR_WRLVL_CNTL_2 0x05060607
  36. #define DDR_DDR_WRLVL_CNTL_3 0x05050505
  37. #define DDR_DDR_CDR1 0x80040000
  38. #define DDR_DDR_CDR2 0x00000001
  39. #define DDR_SDRAM_CLK_CNTL 0x02000000
  40. #define DDR_DDR_ZQ_CNTL 0x89080600
  41. #define DDR_CS0_CONFIG_2 0
  42. #define DDR_SDRAM_CFG_MEM_EN 0x80000000
  43. #define SDRAM_CFG2_D_INIT 0x00000010
  44. #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  45. #define SDRAM_CFG2_FRC_SR 0x80000000
  46. #define SDRAM_CFG_BI 0x00000001
  47. #ifdef CONFIG_RAMBOOT_PBL
  48. #define CONFIG_SYS_FSL_PBL_PBI \
  49. board/freescale/ls1021aiot/ls102xa_pbi.cfg
  50. #endif
  51. #ifdef CONFIG_SD_BOOT
  52. #define CONFIG_SYS_FSL_PBL_RCW \
  53. board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
  54. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  55. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  56. #define CONFIG_SPL_ENV_SUPPORT
  57. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  58. #define CONFIG_SPL_I2C_SUPPORT
  59. #define CONFIG_SPL_WATCHDOG_SUPPORT
  60. #define CONFIG_SPL_MMC_SUPPORT
  61. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
  62. #define CONFIG_SPL_MAX_SIZE 0x1a000
  63. #define CONFIG_SPL_STACK 0x1001d000
  64. #define CONFIG_SPL_PAD_TO 0x1c000
  65. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  66. CONFIG_SYS_MONITOR_LEN)
  67. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  68. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  69. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  70. #define CONFIG_SYS_MONITOR_LEN 0x80000
  71. #endif
  72. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  73. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  74. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  75. /*
  76. * Serial Port
  77. */
  78. #define CONFIG_SYS_NS16550_SERIAL
  79. #define CONFIG_SYS_NS16550_REG_SIZE 1
  80. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  81. /*
  82. * I2C
  83. */
  84. #ifndef CONFIG_DM_I2C
  85. #define CONFIG_SYS_I2C
  86. #else
  87. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  88. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  89. #endif
  90. #define CONFIG_SYS_I2C_MXC
  91. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  92. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  93. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  94. /* EEPROM */
  95. #define CONFIG_ID_EEPROM
  96. #define CONFIG_SYS_I2C_EEPROM_NXID
  97. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  98. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
  99. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  100. /*
  101. * MMC
  102. */
  103. /* SATA */
  104. #define CONFIG_SCSI_AHCI_PLAT
  105. #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  106. #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
  107. #endif
  108. #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
  109. PCI_DEVICE_ID_FREESCALE_AHCI}
  110. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  111. #define CONFIG_SYS_SCSI_MAX_LUN 1
  112. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  113. CONFIG_SYS_SCSI_MAX_LUN)
  114. /* SPI */
  115. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  116. #define CONFIG_SPI_FLASH_SPANSION
  117. #endif
  118. /*
  119. * eTSEC
  120. */
  121. #ifdef CONFIG_TSEC_ENET
  122. #define CONFIG_MII_DEFAULT_TSEC 1
  123. #define CONFIG_TSEC1 1
  124. #define CONFIG_TSEC1_NAME "eTSEC1"
  125. #define CONFIG_TSEC2 1
  126. #define CONFIG_TSEC2_NAME "eTSEC2"
  127. #define TSEC1_PHY_ADDR 1
  128. #define TSEC2_PHY_ADDR 3
  129. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  130. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  131. #define TSEC1_PHYIDX 0
  132. #define TSEC2_PHYIDX 0
  133. #define CONFIG_ETHPRIME "eTSEC2"
  134. #define CONFIG_HAS_ETH0
  135. #define CONFIG_HAS_ETH1
  136. #define CONFIG_HAS_ETH2
  137. #endif
  138. /* PCIe */
  139. #define CONFIG_PCIE1 /* PCIE controler 1 */
  140. #define CONFIG_PCIE2 /* PCIE controler 2 */
  141. #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
  142. #ifdef CONFIG_PCI
  143. #define CONFIG_PCI_SCAN_SHOW
  144. #endif
  145. #define CONFIG_CMDLINE_TAG
  146. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  147. #define CONFIG_LAYERSCAPE_NS_ACCESS
  148. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  149. #define COUNTER_FREQUENCY 12500000
  150. #define CONFIG_HWCONFIG
  151. #define HWCONFIG_BUFFER_SIZE 256
  152. #define CONFIG_FSL_DEVICE_DISABLE
  153. #define CONFIG_EXTRA_ENV_SETTINGS \
  154. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  155. "initrd_high=0xffffffff\0"
  156. /*
  157. * Miscellaneous configurable options
  158. */
  159. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  160. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  161. #define CONFIG_LS102XA_STREAM_ID
  162. #define CONFIG_SYS_INIT_SP_OFFSET \
  163. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  164. #define CONFIG_SYS_INIT_SP_ADDR \
  165. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  166. #ifdef CONFIG_SPL_BUILD
  167. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  168. #else
  169. /* start of monitor */
  170. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  171. #endif
  172. #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
  173. #define CONFIG_OF_BOARD_SETUP
  174. #define CONFIG_OF_STDOUT_VIA_ALIAS
  175. #include <asm/fsl_secure_boot.h>
  176. #endif