kmp204x.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #if defined(CONFIG_KMCOGE4)
  9. #define CONFIG_HOSTNAME "kmcoge4"
  10. #else
  11. #error ("Board not supported")
  12. #endif
  13. #define CONFIG_KMP204X
  14. /* an additionnal option is required for UBI as subpage access is
  15. * supported in u-boot
  16. */
  17. #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
  18. #define CONFIG_NAND_ECC_BCH
  19. /* common KM defines */
  20. #include "km/keymile-common.h"
  21. #define CONFIG_SYS_RAMBOOT
  22. #define CONFIG_RAMBOOT_PBL
  23. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  24. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25. #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
  26. #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
  27. /* High Level Configuration Options */
  28. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  29. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  30. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  31. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  32. #define CONFIG_PCIE1 /* PCIE controller 1 */
  33. #define CONFIG_PCIE3 /* PCIE controller 3 */
  34. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  35. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  36. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  37. /* Environment in SPI Flash */
  38. #define CONFIG_ENV_TOTAL_SIZE 0x020000
  39. #ifndef __ASSEMBLY__
  40. unsigned long get_board_sys_clk(unsigned long dummy);
  41. #endif
  42. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  43. /*
  44. * These can be toggled for performance analysis, otherwise use default.
  45. */
  46. #define CONFIG_SYS_CACHE_STASHING
  47. #define CONFIG_BACKSIDE_L2_CACHE
  48. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  49. #define CONFIG_BTB /* toggle branch predition */
  50. #define CONFIG_ENABLE_36BIT_PHYS
  51. #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
  52. /*
  53. * Config the L3 Cache as L3 SRAM
  54. */
  55. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  56. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
  57. CONFIG_RAMBOOT_TEXT_BASE)
  58. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  59. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  60. #define CONFIG_SYS_DCSRBAR 0xf0000000
  61. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  62. /*
  63. * DDR Setup
  64. */
  65. #define CONFIG_VERY_BIG_RAM
  66. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  67. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  68. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  69. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  70. #define CONFIG_DDR_SPD
  71. #define CONFIG_SYS_SPD_BUS_NUM 0
  72. #define SPD_EEPROM_ADDRESS 0x54
  73. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  74. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  75. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  76. /******************************************************************************
  77. * (PRAM usage)
  78. * ... -------------------------------------------------------
  79. * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
  80. * ... |<------------------- pram -------------------------->|
  81. * ... -------------------------------------------------------
  82. * @END_OF_RAM:
  83. * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
  84. * @CONFIG_KM_PHRAM: address for /var
  85. * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
  86. * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
  87. */
  88. /* size of rootfs in RAM */
  89. #define CONFIG_KM_ROOTFSSIZE 0x0
  90. /* pseudo-non volatile RAM [hex] */
  91. #define CONFIG_KM_PNVRAM 0x80000
  92. /* physical RAM MTD size [hex] */
  93. #define CONFIG_KM_PHRAM 0x100000
  94. /* reserved pram area at the end of memory [hex]
  95. * u-boot reserves some memory for the MP boot page
  96. */
  97. #define CONFIG_KM_RESERVED_PRAM 0x1000
  98. /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
  99. * is not valid yet, which is the case for when u-boot copies itself to RAM
  100. */
  101. #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
  102. /*
  103. * Local Bus Definitions
  104. */
  105. /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
  106. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
  107. /* Nand Flash */
  108. #define CONFIG_NAND_FSL_ELBC
  109. #define CONFIG_SYS_NAND_BASE 0xffa00000
  110. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  111. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  112. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  113. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  114. /* NAND flash config */
  115. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  116. | BR_PS_8 /* Port Size = 8 bit */ \
  117. | BR_MS_FCM /* MSEL = FCM */ \
  118. | BR_V) /* valid */
  119. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
  120. | OR_FCM_BCTLD /* LBCTL not ass */ \
  121. | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
  122. | OR_FCM_RST /* 1 clk read setup */ \
  123. | OR_FCM_PGS /* Large page size */ \
  124. | OR_FCM_CST) /* 0.25 command setup */
  125. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  126. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  127. /* QRIO FPGA */
  128. #define CONFIG_SYS_QRIO_BASE 0xfb000000
  129. #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
  130. #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
  131. | BR_PS_8 /* Port Size 8 bits */ \
  132. | BR_DECC_OFF /* no error corr */ \
  133. | BR_MS_GPCM /* MSEL = GPCM */ \
  134. | BR_V) /* valid */
  135. #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
  136. | OR_GPCM_BCTLD /* no LCTL assert */ \
  137. | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
  138. | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
  139. | OR_GPCM_TRLX /* relaxed tmgs */ \
  140. | OR_GPCM_EAD) /* extra bus clk cycles */
  141. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
  142. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
  143. #define CONFIG_MISC_INIT_F
  144. #define CONFIG_HWCONFIG
  145. /* define to use L1 as initial stack */
  146. #define CONFIG_L1_INIT_RAM
  147. #define CONFIG_SYS_INIT_RAM_LOCK
  148. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  149. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  150. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  151. /* The assembler doesn't like typecast */
  152. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  153. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  154. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  155. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  156. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  157. GENERATED_GBL_DATA_SIZE)
  158. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  159. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  160. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  161. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  162. /* Serial Port - controlled on board with jumper J8
  163. * open - index 2
  164. * shorted - index 1
  165. */
  166. #define CONFIG_SYS_NS16550_SERIAL
  167. #define CONFIG_SYS_NS16550_REG_SIZE 1
  168. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  169. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
  170. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
  171. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
  172. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
  173. #define CONFIG_KM_CONSOLE_TTY "ttyS0"
  174. /* I2C */
  175. /* QRIO GPIOs used for deblocking */
  176. #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
  177. #define KM_I2C_DEBLOCK_SCL 20
  178. #define KM_I2C_DEBLOCK_SDA 21
  179. #define CONFIG_SYS_I2C
  180. #define CONFIG_SYS_I2C_INIT_BOARD
  181. #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
  182. #define CONFIG_SYS_NUM_I2C_BUSES 3
  183. #define CONFIG_SYS_I2C_MAX_HOPS 1
  184. #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
  185. #define CONFIG_I2C_MULTI_BUS
  186. #define CONFIG_I2C_CMD_TREE
  187. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  188. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  189. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  190. #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
  191. {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
  192. {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
  193. }
  194. #ifndef __ASSEMBLY__
  195. void set_sda(int state);
  196. void set_scl(int state);
  197. int get_sda(void);
  198. int get_scl(void);
  199. #endif
  200. #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
  201. /*
  202. * eSPI - Enhanced SPI
  203. */
  204. /*
  205. * General PCI
  206. * Memory space is mapped 1-1, but I/O space must start from 0.
  207. */
  208. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  209. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  210. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  211. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  212. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  213. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  214. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  215. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  216. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  217. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  218. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  219. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  220. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  221. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  222. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
  223. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  224. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
  225. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  226. /* Qman/Bman */
  227. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  228. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  229. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  230. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  231. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  232. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  233. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  234. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  235. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  236. CONFIG_SYS_BMAN_CENA_SIZE)
  237. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  238. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  239. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  240. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  241. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  242. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  243. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  244. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  245. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  246. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  247. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  248. CONFIG_SYS_QMAN_CENA_SIZE)
  249. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  250. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  251. #define CONFIG_SYS_DPAA_FMAN
  252. #define CONFIG_SYS_DPAA_PME
  253. /* Default address of microcode for the Linux Fman driver
  254. * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
  255. * ucode is stored after env, so we got 0x120000.
  256. */
  257. #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
  258. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  259. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  260. #define CONFIG_PCI_INDIRECT_BRIDGE
  261. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  262. /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
  263. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
  264. #define CONFIG_SYS_TBIPA_VALUE 8
  265. #define CONFIG_ETHPRIME "FM1@DTSEC5"
  266. /*
  267. * Environment
  268. */
  269. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  270. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  271. /*
  272. * Hardware Watchdog
  273. */
  274. #define CONFIG_WATCHDOG /* enable CPU watchdog */
  275. #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
  276. #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
  277. /*
  278. * additionnal command line configuration.
  279. */
  280. /*
  281. * For booting Linux, the board info and command line data
  282. * have to be in the first 64 MB of memory, since this is
  283. * the maximum mapped by the Linux kernel during initialization.
  284. */
  285. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
  286. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  287. #ifdef CONFIG_CMD_KGDB
  288. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  289. #endif
  290. #define __USB_PHY_TYPE utmi
  291. #define CONFIG_USB_EHCI_FSL
  292. /*
  293. * Environment Configuration
  294. */
  295. #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
  296. #define CONFIG_KM_DEF_ENV "km-common=empty\0"
  297. #endif
  298. /* architecture specific default bootargs */
  299. #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
  300. /* FIXME: FDT_ADDR is unspecified */
  301. #define CONFIG_KM_DEF_ENV_CPU \
  302. "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
  303. "cramfsloadfdt=" \
  304. "cramfsload ${fdt_addr_r} " \
  305. "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
  306. "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
  307. "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \
  308. "update=" \
  309. "sf probe 0;sf erase 0 +${filesize};" \
  310. "sf write ${load_addr_r} 0 ${filesize};\0" \
  311. "set_fdthigh=true\0" \
  312. "checkfdt=true\0" \
  313. ""
  314. #define CONFIG_HW_ENV_SETTINGS \
  315. "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
  316. "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  317. "usb_dr_mode=host\0"
  318. #define CONFIG_KM_NEW_ENV \
  319. "newenv=sf probe 0;" \
  320. "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
  321. __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
  322. /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
  323. #ifndef CONFIG_KM_DEF_ARCH
  324. #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
  325. #endif
  326. #define CONFIG_EXTRA_ENV_SETTINGS \
  327. CONFIG_KM_DEF_ENV \
  328. CONFIG_KM_DEF_ARCH \
  329. CONFIG_KM_NEW_ENV \
  330. CONFIG_HW_ENV_SETTINGS \
  331. "EEprom_ivm=pca9547:70:9\0" \
  332. ""
  333. /* App2 Local bus */
  334. #define CONFIG_SYS_LBAPP2_BASE 0xE0000000
  335. #define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
  336. #define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
  337. | BR_PS_8 /* Port Size 8 bits */ \
  338. | BR_DECC_OFF /* no error corr */ \
  339. | BR_MS_GPCM /* MSEL = GPCM */ \
  340. | BR_V) /* valid */
  341. #define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
  342. | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
  343. | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
  344. | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
  345. | OR_GPCM_TRLX /* relaxed tmgs */ \
  346. | OR_GPCM_EAD) /* extra bus clk cycles */
  347. /* Local bus app2 Base Address */
  348. #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
  349. /* Local bus app2 Options */
  350. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
  351. #endif /* __CONFIG_H */