km-mpc8309.h 3.9 KB

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  1. /*
  2. * High Level Configuration Options
  3. */
  4. #define CONFIG_E300 1 /* E300 family */
  5. #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
  6. /*
  7. * System Clock Setup
  8. */
  9. #define CONFIG_83XX_CLKIN 66000000
  10. #define CONFIG_SYS_CLK_FREQ 66000000
  11. #define CONFIG_83XX_PCICLK 66000000
  12. /* QE microcode/firmware address */
  13. /* between the u-boot partition and env */
  14. #ifndef CONFIG_SYS_QE_FW_ADDR
  15. #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
  16. #endif
  17. /*
  18. * System IO Config
  19. */
  20. /* 0x14000180 SICR_1 */
  21. #ifndef CONFIG_SYS_SICRL
  22. #define CONFIG_SYS_SICRL (0 \
  23. | SICR_1_UART1_UART1RTS \
  24. | SICR_1_I2C_CKSTOP \
  25. | SICR_1_IRQ_A_IRQ \
  26. | SICR_1_IRQ_B_IRQ \
  27. | SICR_1_GPIO_A_GPIO \
  28. | SICR_1_GPIO_B_GPIO \
  29. | SICR_1_GPIO_C_GPIO \
  30. | SICR_1_GPIO_D_GPIO \
  31. | SICR_1_GPIO_E_GPIO \
  32. | SICR_1_GPIO_F_GPIO \
  33. | SICR_1_USB_A_UART2S \
  34. | SICR_1_USB_B_UART2RTS \
  35. | SICR_1_FEC1_FEC1 \
  36. | SICR_1_FEC2_FEC2 \
  37. )
  38. #endif
  39. /* 0x00080400 SICR_2 */
  40. #define CONFIG_SYS_SICRH (0 \
  41. | SICR_2_FEC3_FEC3 \
  42. | SICR_2_HDLC1_A_HDLC1 \
  43. | SICR_2_ELBC_A_LA \
  44. | SICR_2_ELBC_B_LCLK \
  45. | SICR_2_HDLC2_A_HDLC2 \
  46. | SICR_2_USB_D_GPIO \
  47. | SICR_2_PCI_PCI \
  48. | SICR_2_HDLC1_B_HDLC1 \
  49. | SICR_2_HDLC1_C_HDLC1 \
  50. | SICR_2_HDLC2_B_GPIO \
  51. | SICR_2_HDLC2_C_HDLC2 \
  52. | SICR_2_QUIESCE_B \
  53. )
  54. /* GPR_1 */
  55. #define CONFIG_SYS_GPR1 0x50008060
  56. #define CONFIG_SYS_GP1DIR 0x00000000
  57. #define CONFIG_SYS_GP1ODR 0x00000000
  58. #define CONFIG_SYS_GP2DIR 0xFF000000
  59. #define CONFIG_SYS_GP2ODR 0x00000000
  60. #define CONFIG_SYS_DDRCDR (\
  61. DDRCDR_EN | \
  62. DDRCDR_PZ_MAXZ | \
  63. DDRCDR_NZ_MAXZ | \
  64. DDRCDR_M_ODR)
  65. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
  66. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  67. SDRAM_CFG_32_BE | \
  68. SDRAM_CFG_SREN | \
  69. SDRAM_CFG_HSE)
  70. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  71. #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  72. #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  73. (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  74. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
  75. CSCONFIG_ODT_RD_NEVER | \
  76. CSCONFIG_ODT_WR_ONLY_CURRENT | \
  77. CSCONFIG_ROW_BIT_13 | \
  78. CSCONFIG_COL_BIT_10)
  79. #define CONFIG_SYS_DDR_MODE 0x47860242
  80. #define CONFIG_SYS_DDR_MODE2 0x8080c000
  81. #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  82. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  83. (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  84. (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  85. (0 << TIMING_CFG0_WWT_SHIFT) | \
  86. (0 << TIMING_CFG0_RRT_SHIFT) | \
  87. (0 << TIMING_CFG0_WRT_SHIFT) | \
  88. (0 << TIMING_CFG0_RWT_SHIFT))
  89. #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
  90. (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  91. (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  92. (3 << TIMING_CFG1_WRREC_SHIFT) | \
  93. (7 << TIMING_CFG1_REFREC_SHIFT) | \
  94. (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  95. (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  96. (3 << TIMING_CFG1_PRETOACT_SHIFT))
  97. #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  98. (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  99. (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  100. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  101. (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  102. (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
  103. (5 << TIMING_CFG2_CPO_SHIFT))
  104. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  105. #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
  106. #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
  107. /* EEprom support */
  108. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  109. /* ethernet port connected to piggy (UEC2) */
  110. #define CONFIG_HAS_ETH1
  111. #define CONFIG_UEC_ETH2
  112. #define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
  113. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
  114. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
  115. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  116. #define CONFIG_SYS_UEC2_PHY_ADDR 0
  117. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  118. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100