hsdk-4xd.h 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
  4. * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  5. */
  6. #ifndef _CONFIG_HSDK_H_
  7. #define _CONFIG_HSDK_H_
  8. #include <linux/sizes.h>
  9. /*
  10. * CPU configuration
  11. */
  12. #define NR_CPUS 4
  13. #define ARC_PERIPHERAL_BASE 0xF0000000
  14. #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
  15. #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
  16. /*
  17. * Memory configuration
  18. */
  19. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  20. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
  21. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  22. #define CONFIG_SYS_SDRAM_SIZE SZ_1G
  23. #define CONFIG_SYS_INIT_SP_ADDR \
  24. (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  25. #define CONFIG_SYS_MALLOC_LEN SZ_2M
  26. #define CONFIG_SYS_BOOTM_LEN SZ_128M
  27. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  28. /*
  29. * UART configuration
  30. */
  31. #define CONFIG_SYS_NS16550_SERIAL
  32. #define CONFIG_SYS_NS16550_CLK 33330000
  33. #define CONFIG_SYS_NS16550_MEM32
  34. /*
  35. * Ethernet PHY configuration
  36. */
  37. /*
  38. * USB 1.1 configuration
  39. */
  40. #define CONFIG_USB_OHCI_NEW
  41. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
  42. /*
  43. * Environment settings
  44. */
  45. #define CONFIG_EXTRA_ENV_SETTINGS \
  46. "upgrade=if mmc rescan && " \
  47. "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
  48. "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
  49. "\"Fail to upgrade.\n" \
  50. "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
  51. "; fi\0" \
  52. "core_mask=0xF\0" \
  53. "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
  54. setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
  55. setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
  56. setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
  57. "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
  58. setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
  59. setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
  60. setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
  61. "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
  62. setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
  63. setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
  64. setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
  65. "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
  66. setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
  67. setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
  68. setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
  69. "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
  70. setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
  71. setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
  72. setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
  73. "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
  74. "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
  75. setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
  76. setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
  77. setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
  78. setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
  79. "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
  80. "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
  81. setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
  82. setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
  83. setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
  84. setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
  85. setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
  86. "hsdk_hs48x4=run hsdk_hs47dx4;\0" \
  87. "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
  88. setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
  89. setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
  90. setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
  91. setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
  92. setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
  93. setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
  94. /*
  95. * Environment configuration
  96. */
  97. #define CONFIG_BOOTFILE "uImage"
  98. #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
  99. /* Cli configuration */
  100. #define CONFIG_SYS_CBSIZE SZ_2K
  101. /*
  102. * Callback configuration
  103. */
  104. #endif /* _CONFIG_HSDK_H_ */