hrcon.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. *
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <linux/stringify.h>
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1 /* E300 family */
  14. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  15. /*
  16. * SERDES
  17. */
  18. #define CONFIG_FSL_SERDES
  19. #define CONFIG_FSL_SERDES1 0xe3000
  20. /*
  21. * DDR Setup
  22. */
  23. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  24. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  25. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  26. | DDRCDR_PZ_LOZ \
  27. | DDRCDR_NZ_LOZ \
  28. | DDRCDR_ODT \
  29. | DDRCDR_Q_DRN)
  30. /* 0x7b880001 */
  31. /*
  32. * Manually set up DDR parameters
  33. * consist of one chip NT5TU64M16HG from NANYA
  34. */
  35. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  36. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  37. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  38. | CSCONFIG_ODT_RD_NEVER \
  39. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  40. | CSCONFIG_BANK_BIT_3 \
  41. | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  42. /* 0x80010102 */
  43. #define CONFIG_SYS_DDR_TIMING_3 0
  44. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  45. | (0 << TIMING_CFG0_WRT_SHIFT) \
  46. | (0 << TIMING_CFG0_RRT_SHIFT) \
  47. | (0 << TIMING_CFG0_WWT_SHIFT) \
  48. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  49. | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  50. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  51. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  52. /* 0x00260802 */
  53. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  54. | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  55. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  56. | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  57. | (9 << TIMING_CFG1_REFREC_SHIFT) \
  58. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  59. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  60. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  61. /* 0x26279222 */
  62. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  63. | (4 << TIMING_CFG2_CPO_SHIFT) \
  64. | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  65. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  66. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  67. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  68. | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  69. /* 0x021848c5 */
  70. #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  71. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  72. /* 0x08240100 */
  73. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  74. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  75. | SDRAM_CFG_DBW_16)
  76. /* 0x43100000 */
  77. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  78. #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  79. | (0x0242 << SDRAM_MODE_SD_SHIFT))
  80. /* ODT 150ohm CL=4, AL=0 on SDRAM */
  81. #define CONFIG_SYS_DDR_MODE2 0x00000000
  82. /*
  83. * Memory test
  84. */
  85. /*
  86. * The reserved memory
  87. */
  88. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  89. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  90. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  91. /*
  92. * Initial RAM Base Address Setup
  93. */
  94. #define CONFIG_SYS_INIT_RAM_LOCK 1
  95. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  96. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  97. #define CONFIG_SYS_GBL_DATA_OFFSET \
  98. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  99. /*
  100. * FLASH on the Local Bus
  101. */
  102. #if 1
  103. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  104. #define CONFIG_FLASH_CFI_LEGACY
  105. #define CONFIG_SYS_FLASH_LEGACY_512Kx16
  106. #endif
  107. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  108. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
  109. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  110. #define CONFIG_SYS_MAX_FLASH_SECT 135
  111. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  112. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  113. #define CONFIG_SYS_FPGA_DONE(k) 0x0010
  114. #define CONFIG_SYS_FPGA_COUNT 1
  115. #define CONFIG_SYS_MCLINK_MAX 3
  116. #define CONFIG_SYS_FPGA_PTR \
  117. { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
  118. /*
  119. * Serial Port
  120. */
  121. #define CONFIG_SYS_NS16550_SERIAL
  122. #define CONFIG_SYS_NS16550_REG_SIZE 1
  123. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  124. #define CONFIG_SYS_BAUDRATE_TABLE \
  125. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  126. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  127. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  128. /* Pass open firmware flat tree */
  129. /* I2C */
  130. #define CONFIG_SYS_I2C
  131. #define CONFIG_SYS_I2C_FSL
  132. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  133. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  134. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  135. #define CONFIG_PCA953X /* NXP PCA9554 */
  136. #define CONFIG_PCA9698 /* NXP PCA9698 */
  137. #define CONFIG_SYS_I2C_IHS
  138. #define CONFIG_SYS_I2C_IHS_CH0
  139. #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
  140. #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
  141. #define CONFIG_SYS_I2C_IHS_CH1
  142. #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
  143. #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
  144. #define CONFIG_SYS_I2C_IHS_CH2
  145. #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
  146. #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
  147. #define CONFIG_SYS_I2C_IHS_CH3
  148. #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
  149. #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
  150. #ifdef CONFIG_HRCON_DH
  151. #define CONFIG_SYS_I2C_IHS_DUAL
  152. #define CONFIG_SYS_I2C_IHS_CH0_1
  153. #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
  154. #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
  155. #define CONFIG_SYS_I2C_IHS_CH1_1
  156. #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
  157. #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
  158. #define CONFIG_SYS_I2C_IHS_CH2_1
  159. #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
  160. #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
  161. #define CONFIG_SYS_I2C_IHS_CH3_1
  162. #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
  163. #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
  164. #endif
  165. /*
  166. * Software (bit-bang) I2C driver configuration
  167. */
  168. #define CONFIG_SYS_I2C_SOFT
  169. #define CONFIG_SYS_I2C_SOFT_SPEED 50000
  170. #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
  171. #define I2C_SOFT_DECLARATIONS2
  172. #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
  173. #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
  174. #define I2C_SOFT_DECLARATIONS3
  175. #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
  176. #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
  177. #define I2C_SOFT_DECLARATIONS4
  178. #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
  179. #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
  180. #define I2C_SOFT_DECLARATIONS5
  181. #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
  182. #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
  183. #define I2C_SOFT_DECLARATIONS6
  184. #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
  185. #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
  186. #define I2C_SOFT_DECLARATIONS7
  187. #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
  188. #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
  189. #define I2C_SOFT_DECLARATIONS8
  190. #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
  191. #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
  192. #ifdef CONFIG_HRCON_DH
  193. #define I2C_SOFT_DECLARATIONS9
  194. #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
  195. #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
  196. #define I2C_SOFT_DECLARATIONS10
  197. #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
  198. #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
  199. #define I2C_SOFT_DECLARATIONS11
  200. #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
  201. #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
  202. #define I2C_SOFT_DECLARATIONS12
  203. #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
  204. #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
  205. #endif
  206. #ifdef CONFIG_HRCON_DH
  207. #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
  208. #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
  209. #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
  210. {12, 0x4c} }
  211. #else
  212. #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
  213. #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
  214. #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
  215. {8, 0x4c} }
  216. #endif
  217. #ifndef __ASSEMBLY__
  218. void fpga_gpio_set(unsigned int bus, int pin);
  219. void fpga_gpio_clear(unsigned int bus, int pin);
  220. int fpga_gpio_get(unsigned int bus, int pin);
  221. void fpga_control_set(unsigned int bus, int pin);
  222. void fpga_control_clear(unsigned int bus, int pin);
  223. #endif
  224. #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
  225. #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
  226. #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
  227. #ifdef CONFIG_HRCON_DH
  228. #define I2C_ACTIVE \
  229. do { \
  230. if (I2C_ADAP_HWNR > 7) \
  231. fpga_control_set(I2C_FPGA_IDX, 0x0004); \
  232. else \
  233. fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
  234. } while (0)
  235. #else
  236. #define I2C_ACTIVE { }
  237. #endif
  238. #define I2C_TRISTATE { }
  239. #define I2C_READ \
  240. (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
  241. #define I2C_SDA(bit) \
  242. do { \
  243. if (bit) \
  244. fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
  245. else \
  246. fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
  247. } while (0)
  248. #define I2C_SCL(bit) \
  249. do { \
  250. if (bit) \
  251. fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
  252. else \
  253. fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
  254. } while (0)
  255. #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
  256. /*
  257. * Software (bit-bang) MII driver configuration
  258. */
  259. #define CONFIG_BITBANGMII_MULTI
  260. /*
  261. * OSD Setup
  262. */
  263. #define CONFIG_SYS_OSD_SCREENS 1
  264. #define CONFIG_SYS_DP501_DIFFERENTIAL
  265. #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
  266. #ifdef CONFIG_HRCON_DH
  267. #define CONFIG_SYS_OSD_DH
  268. #endif
  269. /*
  270. * General PCI
  271. * Addresses are mapped 1-1.
  272. */
  273. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  274. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  275. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  276. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  277. #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  278. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  279. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  280. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  281. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  282. /* enable PCIE clock */
  283. #define CONFIG_SYS_SCCR_PCIEXP1CM 1
  284. #define CONFIG_PCI_INDIRECT_BRIDGE
  285. #define CONFIG_PCIE
  286. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  287. #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
  288. /*
  289. * TSEC
  290. */
  291. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  292. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  293. /*
  294. * TSEC ethernet configuration
  295. */
  296. #define CONFIG_TSEC1
  297. #define CONFIG_TSEC1_NAME "eTSEC0"
  298. #define TSEC1_PHY_ADDR 1
  299. #define TSEC1_PHYIDX 0
  300. #define TSEC1_FLAGS TSEC_GIGABIT
  301. /* Options are: eTSEC[0-1] */
  302. #define CONFIG_ETHPRIME "eTSEC0"
  303. /*
  304. * Environment
  305. */
  306. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  307. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  308. /*
  309. * Miscellaneous configurable options
  310. */
  311. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  312. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  313. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  314. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  315. /*
  316. * For booting Linux, the board info and command line data
  317. * have to be in the first 256 MB of memory, since this is
  318. * the maximum mapped by the Linux kernel during initialization.
  319. */
  320. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  321. /*
  322. * Environment Configuration
  323. */
  324. #if defined(CONFIG_TSEC_ENET)
  325. #define CONFIG_HAS_ETH0
  326. #endif
  327. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  328. #define CONFIG_HOSTNAME "hrcon"
  329. #define CONFIG_ROOTPATH "/opt/nfsroot"
  330. #define CONFIG_BOOTFILE "uImage"
  331. #define CONFIG_EXTRA_ENV_SETTINGS \
  332. "netdev=eth0\0" \
  333. "consoledev=ttyS1\0" \
  334. "u-boot=u-boot.bin\0" \
  335. "kernel_addr=1000000\0" \
  336. "fdt_addr=C00000\0" \
  337. "fdtfile=hrcon.dtb\0" \
  338. "load=tftp ${loadaddr} ${u-boot}\0" \
  339. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  340. " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  341. " +${filesize};cp.b ${fileaddr} " \
  342. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  343. "upd=run load update\0" \
  344. #define CONFIG_NFSBOOTCOMMAND \
  345. "setenv bootargs root=/dev/nfs rw " \
  346. "nfsroot=$serverip:$rootpath " \
  347. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  348. "console=$consoledev,$baudrate $othbootargs;" \
  349. "tftp ${kernel_addr} $bootfile;" \
  350. "tftp ${fdt_addr} $fdtfile;" \
  351. "bootm ${kernel_addr} - ${fdt_addr}"
  352. #define CONFIG_MMCBOOTCOMMAND \
  353. "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
  354. "console=$consoledev,$baudrate $othbootargs;" \
  355. "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
  356. "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
  357. "bootm ${kernel_addr} - ${fdt_addr}"
  358. #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
  359. #endif /* __CONFIG_H */