exynos7420-common.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration settings for the Espresso7420 board.
  4. * Copyright (C) 2016 Samsung Electronics
  5. * Thomas Abraham <thomas.ab@samsung.com>
  6. */
  7. #ifndef __CONFIG_EXYNOS7420_COMMON_H
  8. #define __CONFIG_EXYNOS7420_COMMON_H
  9. /* High Level Configuration Options */
  10. #define CONFIG_SAMSUNG /* in a SAMSUNG core */
  11. #define CONFIG_EXYNOS7420 /* Exynos7 Family */
  12. #define CONFIG_S5P
  13. #include <asm/arch/cpu.h> /* get chip and board defs */
  14. #include <linux/sizes.h>
  15. /* Size of malloc() pool before and after relocation */
  16. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
  17. /* Miscellaneous configurable options */
  18. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  19. #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
  20. /* Boot Argument Buffer Size */
  21. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  22. /* select serial console configuration */
  23. /* Timer input clock frequency */
  24. #define COUNTER_FREQUENCY 24000000
  25. /* Device Tree */
  26. #define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
  27. /* IRAM Layout */
  28. #define CONFIG_IRAM_BASE 0x02100000
  29. #define CONFIG_IRAM_SIZE 0x58000
  30. #define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
  31. #define CPU_RELEASE_ADDR secondary_boot_addr
  32. /* select serial console configuration */
  33. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  34. #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  35. #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
  36. #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
  37. #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
  38. #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
  39. #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
  40. #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
  41. #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
  42. #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
  43. #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
  44. #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
  45. #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
  46. #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
  47. #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
  48. #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
  49. #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
  50. /* Configuration of ENV Blocks */
  51. #define BOOT_TARGET_DEVICES(func) \
  52. func(MMC, mmc, 1) \
  53. func(MMC, mmc, 0) \
  54. #ifndef MEM_LAYOUT_ENV_SETTINGS
  55. #define MEM_LAYOUT_ENV_SETTINGS \
  56. "bootm_size=0x10000000\0" \
  57. "kernel_addr_r=0x42000000\0" \
  58. "fdt_addr_r=0x43000000\0" \
  59. "ramdisk_addr_r=0x43300000\0" \
  60. "scriptaddr=0x50000000\0" \
  61. "pxefile_addr_r=0x51000000\0"
  62. #endif
  63. #ifndef EXYNOS_DEVICE_SETTINGS
  64. #define EXYNOS_DEVICE_SETTINGS \
  65. "stdin=serial\0" \
  66. "stdout=serial\0" \
  67. "stderr=serial\0"
  68. #endif
  69. #ifndef EXYNOS_FDTFILE_SETTING
  70. #define EXYNOS_FDTFILE_SETTING
  71. #endif
  72. #define CONFIG_EXTRA_ENV_SETTINGS \
  73. EXYNOS_DEVICE_SETTINGS \
  74. EXYNOS_FDTFILE_SETTING \
  75. MEM_LAYOUT_ENV_SETTINGS
  76. #endif /* __CONFIG_EXYNOS7420_COMMON_H */