corenet_ds.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * Corenet DS style board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #include "../board/freescale/common/ics307_clk.h"
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #ifdef CONFIG_NXP_ESBC
  15. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  16. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  17. #ifdef CONFIG_MTD_RAW_NAND
  18. #define CONFIG_RAMBOOT_NAND
  19. #endif
  20. #define CONFIG_BOOTSCRIPT_COPY_RAM
  21. #else
  22. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  23. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  24. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  25. #if defined(CONFIG_TARGET_P3041DS)
  26. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  27. #elif defined(CONFIG_TARGET_P4080DS)
  28. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  29. #elif defined(CONFIG_TARGET_P5020DS)
  30. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  31. #elif defined(CONFIG_TARGET_P5040DS)
  32. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  33. #endif
  34. #endif
  35. #endif
  36. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  37. /* Set 1M boot space */
  38. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  39. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  40. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  41. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  42. #endif
  43. /* High Level Configuration Options */
  44. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  45. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  47. #endif
  48. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  49. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  50. #define CONFIG_PCIE1 /* PCIE controller 1 */
  51. #define CONFIG_PCIE2 /* PCIE controller 2 */
  52. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  53. #if defined(CONFIG_SPIFLASH)
  54. #elif defined(CONFIG_SDCARD)
  55. #define CONFIG_FSL_FIXED_MMC_LOCATION
  56. #endif
  57. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  58. /*
  59. * These can be toggled for performance analysis, otherwise use default.
  60. */
  61. #define CONFIG_SYS_CACHE_STASHING
  62. #define CONFIG_BACKSIDE_L2_CACHE
  63. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  64. #define CONFIG_BTB /* toggle branch predition */
  65. #define CONFIG_DDR_ECC
  66. #ifdef CONFIG_DDR_ECC
  67. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  68. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  69. #endif
  70. #define CONFIG_ENABLE_36BIT_PHYS
  71. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  72. /*
  73. * Config the L3 Cache as L3 SRAM
  74. */
  75. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  76. #ifdef CONFIG_PHYS_64BIT
  77. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  78. #else
  79. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  80. #endif
  81. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  82. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  83. #ifdef CONFIG_PHYS_64BIT
  84. #define CONFIG_SYS_DCSRBAR 0xf0000000
  85. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  86. #endif
  87. /* EEPROM */
  88. #define CONFIG_ID_EEPROM
  89. #define CONFIG_SYS_I2C_EEPROM_NXID
  90. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  91. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  92. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  93. /*
  94. * DDR Setup
  95. */
  96. #define CONFIG_VERY_BIG_RAM
  97. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  98. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  99. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  100. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  101. #define CONFIG_DDR_SPD
  102. #define CONFIG_SYS_SPD_BUS_NUM 1
  103. #define SPD_EEPROM_ADDRESS1 0x51
  104. #define SPD_EEPROM_ADDRESS2 0x52
  105. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  106. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  107. /*
  108. * Local Bus Definitions
  109. */
  110. /* Set the local bus clock 1/8 of platform clock */
  111. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  112. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
  113. #ifdef CONFIG_PHYS_64BIT
  114. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  115. #else
  116. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  117. #endif
  118. #define CONFIG_SYS_FLASH_BR_PRELIM \
  119. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
  120. | BR_PS_16 | BR_V)
  121. #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  122. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  123. #define CONFIG_SYS_BR1_PRELIM \
  124. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  125. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  126. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  127. #ifdef CONFIG_PHYS_64BIT
  128. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  129. #else
  130. #define PIXIS_BASE_PHYS PIXIS_BASE
  131. #endif
  132. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  133. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  134. #define PIXIS_LBMAP_SWITCH 7
  135. #define PIXIS_LBMAP_MASK 0xf0
  136. #define PIXIS_LBMAP_SHIFT 4
  137. #define PIXIS_LBMAP_ALTBANK 0x40
  138. #define CONFIG_SYS_FLASH_QUIET_TEST
  139. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  140. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  141. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  142. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  143. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  144. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  145. #if defined(CONFIG_RAMBOOT_PBL)
  146. #define CONFIG_SYS_RAMBOOT
  147. #endif
  148. /* Nand Flash */
  149. #ifdef CONFIG_NAND_FSL_ELBC
  150. #define CONFIG_SYS_NAND_BASE 0xffa00000
  151. #ifdef CONFIG_PHYS_64BIT
  152. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  153. #else
  154. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  155. #endif
  156. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  157. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  158. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  159. /* NAND flash config */
  160. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  161. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  162. | BR_PS_8 /* Port Size = 8 bit */ \
  163. | BR_MS_FCM /* MSEL = FCM */ \
  164. | BR_V) /* valid */
  165. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  166. | OR_FCM_PGS /* Large Page*/ \
  167. | OR_FCM_CSCT \
  168. | OR_FCM_CST \
  169. | OR_FCM_CHT \
  170. | OR_FCM_SCY_1 \
  171. | OR_FCM_TRLX \
  172. | OR_FCM_EHTR)
  173. #ifdef CONFIG_MTD_RAW_NAND
  174. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  175. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  176. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  177. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  178. #else
  179. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  180. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  181. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  182. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  183. #endif
  184. #else
  185. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  186. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  187. #endif /* CONFIG_NAND_FSL_ELBC */
  188. #define CONFIG_SYS_FLASH_EMPTY_INFO
  189. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  190. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  191. #define CONFIG_HWCONFIG
  192. /* define to use L1 as initial stack */
  193. #define CONFIG_L1_INIT_RAM
  194. #define CONFIG_SYS_INIT_RAM_LOCK
  195. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  196. #ifdef CONFIG_PHYS_64BIT
  197. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  198. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  199. /* The assembler doesn't like typecast */
  200. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  201. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  202. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  203. #else
  204. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  205. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  206. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  207. #endif
  208. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  209. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  210. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  211. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  212. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  213. /* Serial Port - controlled on board with jumper J8
  214. * open - index 2
  215. * shorted - index 1
  216. */
  217. #define CONFIG_SYS_NS16550_SERIAL
  218. #define CONFIG_SYS_NS16550_REG_SIZE 1
  219. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  220. #define CONFIG_SYS_BAUDRATE_TABLE \
  221. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  222. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  223. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  224. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  225. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  226. /* I2C */
  227. #ifndef CONFIG_DM_I2C
  228. #define CONFIG_SYS_I2C
  229. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  230. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  231. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  232. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  233. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  234. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  235. #else
  236. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  237. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  238. #endif
  239. #define CONFIG_SYS_I2C_FSL
  240. /*
  241. * RapidIO
  242. */
  243. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  244. #ifdef CONFIG_PHYS_64BIT
  245. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  246. #else
  247. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  248. #endif
  249. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  250. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  251. #ifdef CONFIG_PHYS_64BIT
  252. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  253. #else
  254. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  255. #endif
  256. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  257. /*
  258. * for slave u-boot IMAGE instored in master memory space,
  259. * PHYS must be aligned based on the SIZE
  260. */
  261. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  262. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  263. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  264. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  265. /*
  266. * for slave UCODE and ENV instored in master memory space,
  267. * PHYS must be aligned based on the SIZE
  268. */
  269. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  270. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  271. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  272. /* slave core release by master*/
  273. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  274. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  275. /*
  276. * SRIO_PCIE_BOOT - SLAVE
  277. */
  278. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  279. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  280. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  281. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  282. #endif
  283. /*
  284. * eSPI - Enhanced SPI
  285. */
  286. /*
  287. * General PCI
  288. * Memory space is mapped 1-1, but I/O space must start from 0.
  289. */
  290. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  291. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  292. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  293. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  294. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  295. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  296. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  297. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  298. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  299. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  300. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  301. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  302. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  303. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  304. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  305. /* controller 4, Base address 203000 */
  306. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  307. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  308. /* Qman/Bman */
  309. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  310. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  311. #ifdef CONFIG_PHYS_64BIT
  312. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  313. #else
  314. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  315. #endif
  316. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  317. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  318. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  319. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  320. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  321. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  322. CONFIG_SYS_BMAN_CENA_SIZE)
  323. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  324. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  325. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  326. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  327. #ifdef CONFIG_PHYS_64BIT
  328. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  329. #else
  330. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  331. #endif
  332. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  333. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  334. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  335. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  336. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  337. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  338. CONFIG_SYS_QMAN_CENA_SIZE)
  339. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  340. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  341. #define CONFIG_SYS_DPAA_FMAN
  342. #define CONFIG_SYS_DPAA_PME
  343. /* Default address of microcode for the Linux Fman driver */
  344. #if defined(CONFIG_SPIFLASH)
  345. /*
  346. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  347. * env, so we got 0x110000.
  348. */
  349. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  350. #elif defined(CONFIG_SDCARD)
  351. /*
  352. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  353. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  354. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  355. */
  356. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  357. #elif defined(CONFIG_MTD_RAW_NAND)
  358. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  359. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  360. /*
  361. * Slave has no ucode locally, it can fetch this from remote. When implementing
  362. * in two corenet boards, slave's ucode could be stored in master's memory
  363. * space, the address can be mapped from slave TLB->slave LAW->
  364. * slave SRIO or PCIE outbound window->master inbound window->
  365. * master LAW->the ucode address in master's memory space.
  366. */
  367. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  368. #else
  369. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  370. #endif
  371. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  372. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  373. #ifdef CONFIG_PCI
  374. #if !defined(CONFIG_DM_PCI)
  375. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  376. #define CONFIG_PCI_INDIRECT_BRIDGE
  377. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  378. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  379. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  380. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  381. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  382. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  383. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  384. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  385. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  386. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  387. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  388. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  389. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  390. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  391. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  392. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  393. #endif
  394. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  395. #endif /* CONFIG_PCI */
  396. /* SATA */
  397. #ifdef CONFIG_FSL_SATA_V2
  398. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  399. #define CONFIG_SATA1
  400. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  401. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  402. #define CONFIG_SATA2
  403. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  404. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  405. #define CONFIG_LBA48
  406. #endif
  407. #ifdef CONFIG_FMAN_ENET
  408. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
  409. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
  410. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
  411. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
  412. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
  413. #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
  414. #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
  415. #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
  416. #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
  417. #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
  418. #define CONFIG_SYS_TBIPA_VALUE 8
  419. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  420. #endif
  421. /*
  422. * Environment
  423. */
  424. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  425. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  426. /*
  427. * USB
  428. */
  429. #define CONFIG_HAS_FSL_DR_USB
  430. #define CONFIG_HAS_FSL_MPH_USB
  431. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  432. #define CONFIG_USB_EHCI_FSL
  433. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  434. #endif
  435. #ifdef CONFIG_MMC
  436. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  437. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  438. #endif
  439. /*
  440. * Miscellaneous configurable options
  441. */
  442. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  443. /*
  444. * For booting Linux, the board info and command line data
  445. * have to be in the first 64 MB of memory, since this is
  446. * the maximum mapped by the Linux kernel during initialization.
  447. */
  448. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  449. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  450. #ifdef CONFIG_CMD_KGDB
  451. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  452. #endif
  453. /*
  454. * Environment Configuration
  455. */
  456. #define CONFIG_ROOTPATH "/opt/nfsroot"
  457. #define CONFIG_BOOTFILE "uImage"
  458. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  459. /* default location for tftp and bootm */
  460. #define CONFIG_LOADADDR 1000000
  461. #ifdef CONFIG_TARGET_P4080DS
  462. #define __USB_PHY_TYPE ulpi
  463. #else
  464. #define __USB_PHY_TYPE utmi
  465. #endif
  466. #define CONFIG_EXTRA_ENV_SETTINGS \
  467. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  468. "bank_intlv=cs0_cs1;" \
  469. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  470. "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  471. "netdev=eth0\0" \
  472. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  473. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  474. "tftpflash=tftpboot $loadaddr $uboot && " \
  475. "protect off $ubootaddr +$filesize && " \
  476. "erase $ubootaddr +$filesize && " \
  477. "cp.b $loadaddr $ubootaddr $filesize && " \
  478. "protect on $ubootaddr +$filesize && " \
  479. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  480. "consoledev=ttyS0\0" \
  481. "ramdiskaddr=2000000\0" \
  482. "ramdiskfile=p4080ds/ramdisk.uboot\0" \
  483. "fdtaddr=1e00000\0" \
  484. "fdtfile=p4080ds/p4080ds.dtb\0" \
  485. "bdev=sda3\0"
  486. #define CONFIG_HDBOOT \
  487. "setenv bootargs root=/dev/$bdev rw " \
  488. "console=$consoledev,$baudrate $othbootargs;" \
  489. "tftp $loadaddr $bootfile;" \
  490. "tftp $fdtaddr $fdtfile;" \
  491. "bootm $loadaddr - $fdtaddr"
  492. #define CONFIG_NFSBOOTCOMMAND \
  493. "setenv bootargs root=/dev/nfs rw " \
  494. "nfsroot=$serverip:$rootpath " \
  495. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  496. "console=$consoledev,$baudrate $othbootargs;" \
  497. "tftp $loadaddr $bootfile;" \
  498. "tftp $fdtaddr $fdtfile;" \
  499. "bootm $loadaddr - $fdtaddr"
  500. #define CONFIG_RAMBOOTCOMMAND \
  501. "setenv bootargs root=/dev/ram rw " \
  502. "console=$consoledev,$baudrate $othbootargs;" \
  503. "tftp $ramdiskaddr $ramdiskfile;" \
  504. "tftp $loadaddr $bootfile;" \
  505. "tftp $fdtaddr $fdtfile;" \
  506. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  507. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  508. #include <asm/fsl_secure_boot.h>
  509. #endif /* __CONFIG_H */