controlcenterd.h 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352
  1. /*
  2. * (C) Copyright 2013
  3. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4. *
  5. * based on P1022DS.h
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. #include <linux/stringify.h>
  28. #ifdef CONFIG_SDCARD
  29. #define CONFIG_RAMBOOT_SDCARD
  30. #endif
  31. #ifdef CONFIG_SPIFLASH
  32. #define CONFIG_RAMBOOT_SPIFLASH
  33. #endif
  34. /* High Level Configuration Options */
  35. #define CONFIG_CONTROLCENTERD
  36. #define CONFIG_ENABLE_36BIT_PHYS
  37. #define CONFIG_L2_CACHE
  38. #define CONFIG_BTB
  39. #define CONFIG_SYS_CLK_FREQ 66666600
  40. #define CONFIG_DDR_CLK_FREQ 66666600
  41. #define CONFIG_SYS_RAMBOOT
  42. #ifdef CONFIG_TRAILBLAZER
  43. #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
  44. #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  45. /*
  46. * Config the L2 Cache
  47. */
  48. #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
  49. #ifdef CONFIG_PHYS_64BIT
  50. #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
  51. #else
  52. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  53. #endif
  54. #define CONFIG_SYS_L2_SIZE (256 << 10)
  55. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  56. #else /* CONFIG_TRAILBLAZER */
  57. #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  58. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  59. #endif /* CONFIG_TRAILBLAZER */
  60. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  61. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  62. /*
  63. * Memory map
  64. *
  65. * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
  66. * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
  67. * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
  68. *
  69. * Localbus non-cacheable
  70. * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
  71. * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
  72. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  73. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  74. */
  75. #define CONFIG_SYS_INIT_RAM_LOCK
  76. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  77. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
  78. #define CONFIG_SYS_GBL_DATA_OFFSET \
  79. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  80. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  81. #ifdef CONFIG_TRAILBLAZER
  82. /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
  83. #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
  84. #else
  85. #define CONFIG_SYS_CCSRBAR 0xffe00000
  86. #endif
  87. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  88. #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
  89. /*
  90. * DDR Setup
  91. */
  92. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  93. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  94. #define CONFIG_SYS_SDRAM_SIZE 1024
  95. #define CONFIG_VERY_BIG_RAM
  96. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  97. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  98. #ifdef CONFIG_TRAILBLAZER
  99. #define CONFIG_SPD_EEPROM
  100. #define SPD_EEPROM_ADDRESS 0x52
  101. /*#define CONFIG_FSL_DDR_INTERACTIVE*/
  102. #endif
  103. /*
  104. * Local Bus Definitions
  105. */
  106. #define CONFIG_SYS_ELBC_BASE 0xe0000000
  107. #ifdef CONFIG_PHYS_64BIT
  108. #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
  109. #else
  110. #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
  111. #endif
  112. #define CONFIG_UART_BR_PRELIM \
  113. (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
  114. #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
  115. #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
  116. #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
  117. #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
  118. #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
  119. /*
  120. * Serial Port
  121. */
  122. #define CONFIG_SYS_NS16550_SERIAL
  123. #define CONFIG_SYS_NS16550_REG_SIZE 1
  124. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  125. #define CONFIG_SYS_BAUDRATE_TABLE \
  126. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  127. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  128. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  129. /*
  130. * I2C
  131. */
  132. #define CONFIG_SYS_I2C
  133. #define CONFIG_SYS_I2C_FSL
  134. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  135. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  136. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  137. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  138. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  139. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  140. #define CONFIG_PCA9698 /* NXP PCA9698 */
  141. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  142. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  143. /*
  144. * MMC
  145. */
  146. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  147. #ifndef CONFIG_TRAILBLAZER
  148. /*
  149. * Video
  150. */
  151. #define CONFIG_FSL_DIU_FB
  152. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
  153. /*
  154. * General PCI
  155. * Memory space is mapped 1-1, but I/O space must start from 0.
  156. */
  157. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  158. #define CONFIG_PCI_INDIRECT_BRIDGE
  159. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  160. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  161. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  162. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  163. #ifdef CONFIG_PHYS_64BIT
  164. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  165. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  166. #else
  167. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  168. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  169. #endif
  170. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  171. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  172. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  173. #ifdef CONFIG_PHYS_64BIT
  174. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  175. #else
  176. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  177. #endif
  178. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  179. /*
  180. * SATA
  181. */
  182. #define CONFIG_LBA48
  183. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  184. #define CONFIG_SATA1
  185. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  186. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  187. #define CONFIG_SATA2
  188. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  189. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  190. /*
  191. * Ethernet
  192. */
  193. #define CONFIG_TSECV2
  194. #define CONFIG_TSEC1 1
  195. #define CONFIG_TSEC1_NAME "eTSEC1"
  196. #define CONFIG_TSEC2 1
  197. #define CONFIG_TSEC2_NAME "eTSEC2"
  198. #define TSEC1_PHY_ADDR 0
  199. #define TSEC2_PHY_ADDR 1
  200. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  201. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  202. #define TSEC1_PHYIDX 0
  203. #define TSEC2_PHYIDX 0
  204. #define CONFIG_ETHPRIME "eTSEC1"
  205. /*
  206. * USB
  207. */
  208. #define CONFIG_HAS_FSL_DR_USB
  209. #define CONFIG_USB_EHCI_FSL
  210. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  211. #endif /* CONFIG_TRAILBLAZER */
  212. /*
  213. * Environment
  214. */
  215. #if defined(CONFIG_TRAILBLAZER)
  216. #elif defined(CONFIG_RAMBOOT_SDCARD)
  217. #define CONFIG_FSL_FIXED_MMC_LOCATION
  218. #endif
  219. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  220. #ifndef CONFIG_TRAILBLAZER
  221. /*
  222. * Board initialisation callbacks
  223. */
  224. #endif /* CONFIG_TRAILBLAZER */
  225. /*
  226. * Miscellaneous configurable options
  227. */
  228. #define CONFIG_HW_WATCHDOG
  229. #define CONFIG_LOADS_ECHO
  230. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  231. /*
  232. * For booting Linux, the board info and command line data
  233. * have to be in the first 64 MB of memory, since this is
  234. * the maximum mapped by the Linux kernel during initialization.
  235. */
  236. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
  237. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  238. /*
  239. * Environment Configuration
  240. */
  241. #ifdef CONFIG_TRAILBLAZER
  242. #define CONFIG_EXTRA_ENV_SETTINGS \
  243. "mp_holdoff=1\0"
  244. #else
  245. #define CONFIG_HOSTNAME "controlcenterd"
  246. #define CONFIG_ROOTPATH "/opt/nfsroot"
  247. #define CONFIG_BOOTFILE "uImage"
  248. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
  249. #define CONFIG_LOADADDR 1000000
  250. #define CONFIG_EXTRA_ENV_SETTINGS \
  251. "netdev=eth0\0" \
  252. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  253. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  254. "tftpflash=tftpboot $loadaddr $uboot && " \
  255. "protect off $ubootaddr +$filesize && " \
  256. "erase $ubootaddr +$filesize && " \
  257. "cp.b $loadaddr $ubootaddr $filesize && " \
  258. "protect on $ubootaddr +$filesize && " \
  259. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  260. "consoledev=ttyS1\0" \
  261. "ramdiskaddr=2000000\0" \
  262. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  263. "fdtaddr=1e00000\0" \
  264. "fdtfile=controlcenterd.dtb\0" \
  265. "bdev=sda3\0"
  266. /* these are used and NUL-terminated in env_default.h */
  267. #define CONFIG_NFSBOOTCOMMAND \
  268. "setenv bootargs root=/dev/nfs rw " \
  269. "nfsroot=$serverip:$rootpath " \
  270. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  271. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  272. "tftp $loadaddr $bootfile;" \
  273. "tftp $fdtaddr $fdtfile;" \
  274. "bootm $loadaddr - $fdtaddr"
  275. #define CONFIG_RAMBOOTCOMMAND \
  276. "setenv bootargs root=/dev/ram rw " \
  277. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  278. "tftp $ramdiskaddr $ramdiskfile;" \
  279. "tftp $loadaddr $bootfile;" \
  280. "tftp $fdtaddr $fdtfile;" \
  281. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  282. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  283. #endif /* CONFIG_TRAILBLAZER */
  284. #endif