capricorn-common.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017-2018 NXP
  4. * Copyright 2019 Siemens AG
  5. */
  6. #ifndef __IMX8X_CAPRICORN_H
  7. #define __IMX8X_CAPRICORN_H
  8. #include <linux/sizes.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include "siemens-env-common.h"
  11. #include "siemens-ccp-common.h"
  12. /* SPL config */
  13. #ifdef CONFIG_SPL_BUILD
  14. #define CONFIG_SPL_MAX_SIZE (124 * 1024)
  15. #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
  16. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  17. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
  18. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  19. #define CONFIG_SPL_STACK 0x013E000
  20. #define CONFIG_SPL_BSS_START_ADDR 0x00128000
  21. #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
  22. #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
  23. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
  24. #define CONFIG_MALLOC_F_ADDR 0x00120000
  25. #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  26. #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  27. #endif /* CONFIG_SPL_BUILD */
  28. #define CONFIG_FACTORYSET
  29. #undef CONFIG_IDENT_STRING
  30. #define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
  31. #define CONFIG_REMAKE_ELF
  32. /* ENET Config */
  33. #define CONFIG_FEC_XCV_TYPE RMII
  34. #define FEC_QUIRK_ENET_MAC
  35. /* ENET1 connects to base board and MUX with ESAI */
  36. #define CONFIG_FEC_ENET_DEV 1
  37. #define CONFIG_FEC_MXC_PHYADDR 0x0
  38. #define CONFIG_ETHPRIME "eth1"
  39. /* I2C Configuration */
  40. #ifndef CONFIG_SPL_BUILD
  41. #define CONFIG_SYS_I2C_SPEED 400000
  42. /* EEPROM */
  43. #define EEPROM_I2C_BUS 0 /* I2C0 */
  44. #define EEPROM_I2C_ADDR 0x50
  45. /* PCA9552 */
  46. #define PCA9552_1_I2C_BUS 1 /* I2C1 */
  47. #define PCA9552_1_I2C_ADDR 0x60
  48. #endif /* !CONFIG_SPL_BUILD */
  49. /* AHAB */
  50. #ifdef CONFIG_AHAB_BOOT
  51. #define AHAB_ENV "sec_boot=yes\0"
  52. #else
  53. #define AHAB_ENV "sec_boot=no\0"
  54. #endif
  55. #define MFG_ENV_SETTINGS_DEFAULT \
  56. "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  57. "rdinit=/linuxrc " \
  58. "clk_ignore_unused "\
  59. "\0" \
  60. "kboot=booti\0"\
  61. "bootcmd_mfg=run mfgtool_args;" \
  62. "if iminfo ${initrd_addr}; then " \
  63. "if test ${tee} = yes; then " \
  64. "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
  65. "else " \
  66. "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
  67. "fi; " \
  68. "else " \
  69. "echo \"Run fastboot ...\"; fastboot 0; " \
  70. "fi;\0"
  71. /* Boot M4 */
  72. #define M4_BOOT_ENV \
  73. "m4_0_image=m4_0.bin\0" \
  74. "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
  75. "${loadaddr} ${m4_0_image}\0" \
  76. "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  77. #define CONFIG_MFG_ENV_SETTINGS \
  78. MFG_ENV_SETTINGS_DEFAULT \
  79. "initrd_addr=0x83100000\0" \
  80. "initrd_high=0xffffffffffffffff\0" \
  81. "emmc_dev=0\0"
  82. /* Initial environment variables */
  83. #define CONFIG_EXTRA_ENV_SETTINGS \
  84. CONFIG_MFG_ENV_SETTINGS \
  85. M4_BOOT_ENV \
  86. AHAB_ENV \
  87. ENV_COMMON \
  88. "script=boot.scr\0" \
  89. "image=Image\0" \
  90. "panel=NULL\0" \
  91. "console=ttyLP2\0" \
  92. "fdt_addr=0x83000000\0" \
  93. "fdt_high=0xffffffffffffffff\0" \
  94. "cntr_addr=0x88000000\0" \
  95. "cntr_file=os_cntr_signed.bin\0" \
  96. "initrd_addr=0x83800000\0" \
  97. "initrd_high=0xffffffffffffffff\0" \
  98. "netdev=eth0\0" \
  99. "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
  100. "hostname=capricorn\0" \
  101. ENV_EMMC \
  102. ENV_NET
  103. #define CONFIG_BOOTCOMMAND \
  104. "if usrbutton; then " \
  105. "run flash_self_test; " \
  106. "reset; " \
  107. "fi;" \
  108. "run flash_self;" \
  109. "reset;"
  110. /* Default location for tftp and bootm */
  111. #define CONFIG_LOADADDR 0x80280000
  112. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  113. #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
  114. /* On CCP board, USDHC1 is for eMMC */
  115. #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
  116. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  117. /* Size of malloc() pool */
  118. #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
  119. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  120. #define PHYS_SDRAM_1 0x80000000
  121. #define PHYS_SDRAM_2 0x880000000
  122. /* DDR3 board total DDR is 1 GB */
  123. #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
  124. #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
  125. /* Console buffer and boot args */
  126. #define CONFIG_SYS_CBSIZE 2048
  127. #define CONFIG_SYS_MAXARGS 64
  128. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  129. /* Generic Timer Definitions */
  130. #define COUNTER_FREQUENCY 8000000 /* 8MHz */
  131. #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
  132. #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
  133. #endif /* __IMX8X_CAPRICORN_H */