at91sam9m10g45ek.h 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  12. /* ARM asynchronous clock */
  13. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  14. #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
  15. #define CONFIG_AT91SAM9M10G45EK
  16. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  17. #define CONFIG_SETUP_MEMORY_TAGS
  18. #define CONFIG_INITRD_TAG
  19. #define CONFIG_SKIP_LOWLEVEL_INIT
  20. /* general purpose I/O */
  21. #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  22. /* LCD */
  23. #define LCD_BPP LCD_COLOR8
  24. #define CONFIG_LCD_LOGO
  25. #undef LCD_TEST_PATTERN
  26. #define CONFIG_LCD_INFO
  27. #define CONFIG_LCD_INFO_BELOW_LOGO
  28. #define CONFIG_ATMEL_LCD
  29. #define CONFIG_ATMEL_LCD_RGB565
  30. /* board specific(not enough SRAM) */
  31. #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
  32. /*
  33. * BOOTP options
  34. */
  35. #define CONFIG_BOOTP_BOOTFILESIZE
  36. /* SDRAM */
  37. #define CONFIG_SYS_SDRAM_BASE 0x70000000
  38. #define CONFIG_SYS_SDRAM_SIZE 0x08000000
  39. #define CONFIG_SYS_INIT_SP_ADDR \
  40. (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  41. /* NAND flash */
  42. #ifdef CONFIG_CMD_NAND
  43. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  44. #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  45. #define CONFIG_SYS_NAND_DBW_8
  46. /* our ALE is AD21 */
  47. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  48. /* our CLE is AD22 */
  49. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  50. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
  51. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
  52. #endif
  53. /* Ethernet */
  54. #define CONFIG_RESET_PHY_R
  55. #define CONFIG_AT91_WANTS_COMMON_PHY
  56. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  57. #ifdef CONFIG_NAND_BOOT
  58. /* bootstrap + u-boot + env in nandflash */
  59. #define CONFIG_BOOTCOMMAND \
  60. "nand read 0x70000000 0x200000 0x300000;" \
  61. "bootm 0x70000000"
  62. #elif CONFIG_SD_BOOT
  63. /* bootstrap + u-boot + env + linux in mmc */
  64. #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
  65. "fatload mmc 0:1 0x72000000 zImage; " \
  66. "bootz 0x72000000 - 0x71000000"
  67. #endif
  68. /*
  69. * Size of malloc() pool
  70. */
  71. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
  72. /* Defines for SPL */
  73. #define CONFIG_SPL_MAX_SIZE 0x010000
  74. #define CONFIG_SPL_STACK 0x310000
  75. #define CONFIG_SYS_MONITOR_LEN 0x80000
  76. #ifdef CONFIG_SD_BOOT
  77. #define CONFIG_SPL_BSS_START_ADDR 0x70000000
  78. #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
  79. #define CONFIG_SYS_SPL_MALLOC_START 0x70080000
  80. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
  81. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  82. #elif CONFIG_NAND_BOOT
  83. #define CONFIG_SPL_NAND_SOFTECC
  84. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  85. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
  86. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  87. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  88. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  89. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  90. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  91. #define CONFIG_SYS_NAND_ECCSIZE 256
  92. #define CONFIG_SYS_NAND_ECCBYTES 3
  93. #define CONFIG_SYS_NAND_OOBSIZE 64
  94. #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
  95. 48, 49, 50, 51, 52, 53, 54, 55, \
  96. 56, 57, 58, 59, 60, 61, 62, 63, }
  97. #endif
  98. #define CONFIG_SPL_ATMEL_SIZE
  99. #define CONFIG_SYS_MASTER_CLOCK 132096000
  100. #define CONFIG_SYS_AT91_PLLA 0x20c73f03
  101. #define CONFIG_SYS_MCKR 0x1301
  102. #define CONFIG_SYS_MCKR_CSS 0x1302
  103. #endif