at91rm9200ek.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
  4. *
  5. * based on previous work by
  6. *
  7. * Ulf Samuelsson <ulf@atmel.com>
  8. * Rick Bronson <rick@efn.org>
  9. *
  10. * Configuration settings for the AT91RM9200EK board.
  11. */
  12. #ifndef __AT91RM9200EK_CONFIG_H__
  13. #define __AT91RM9200EK_CONFIG_H__
  14. #include <linux/sizes.h>
  15. /*
  16. * set some initial configurations depending on configure target
  17. *
  18. * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
  19. * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
  20. * initialisation was done by some preloader
  21. */
  22. #ifdef CONFIG_RAMBOOT
  23. #define CONFIG_SKIP_LOWLEVEL_INIT
  24. #endif
  25. /*
  26. * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
  27. * AT91C_MAIN_CLOCK is the frequency of PLLA output
  28. * AT91C_MASTER_CLOCK is the peripherial clock
  29. * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
  30. * set in arch/arm/cpu/arm920t/at91/timer.c)
  31. * CONFIG_SYS_HZ is the tick rate for timer tc0
  32. */
  33. #define AT91C_XTAL_CLOCK 18432000
  34. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  35. #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
  36. #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
  37. #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
  38. /* CPU configuration */
  39. #define CONFIG_AT91RM9200
  40. #define CONFIG_AT91RM9200EK
  41. #define USE_920T_MMU
  42. #include <asm/hardware.h> /* needed for port definitions */
  43. #define CONFIG_CMDLINE_TAG
  44. #define CONFIG_SETUP_MEMORY_TAGS
  45. #define CONFIG_INITRD_TAG
  46. /*
  47. * Memory Configuration
  48. */
  49. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  50. #define CONFIG_SYS_SDRAM_SIZE SZ_32M
  51. /*
  52. * LowLevel Init
  53. */
  54. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  55. #define CONFIG_SYS_USE_MAIN_OSCILLATOR
  56. /* flash */
  57. #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  58. #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  59. /* clocks */
  60. #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
  61. #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  62. /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  63. #define CONFIG_SYS_MCKR_VAL 0x00000202
  64. /* sdram */
  65. #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  66. #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  67. #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  68. #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  69. #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  70. #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
  71. #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
  72. #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
  73. #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
  74. #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  75. #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  76. #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  77. #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
  78. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  79. /*
  80. * Hardware drivers
  81. */
  82. /*
  83. * Choose a USART for serial console
  84. * CONFIG_DBGU is DBGU unit on J10
  85. * CONFIG_USART1 is USART1 on J14
  86. */
  87. #define CONFIG_USART_BASE ATMEL_BASE_DBGU
  88. #define CONFIG_USART_ID 0/* ignored in arm */
  89. /*
  90. * Network Driver Setting
  91. */
  92. #define CONFIG_DRIVER_AT91EMAC
  93. #define CONFIG_SYS_RX_ETH_BUFFER 16
  94. #define CONFIG_RMII
  95. /*
  96. * NOR Flash
  97. */
  98. #define CONFIG_SYS_FLASH_BASE 0x10000000
  99. #define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
  100. #define PHYS_FLASH_SIZE SZ_8M
  101. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  102. #define CONFIG_SYS_MAX_FLASH_SECT 256
  103. /*
  104. * USB Config
  105. */
  106. #define CONFIG_USB_ATMEL 1
  107. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  108. #define CONFIG_USB_OHCI_NEW 1
  109. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  110. #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE
  111. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
  112. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  113. /*
  114. * Environment Settings
  115. */
  116. /*
  117. * after u-boot.bin
  118. */
  119. /* The following #defines are needed to get flash environment right */
  120. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  121. #define CONFIG_SYS_MONITOR_LEN SZ_256K
  122. /*
  123. * Boot option
  124. */
  125. /* default load address */
  126. #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
  127. /*
  128. * Shell Settings
  129. */
  130. /*
  131. * Size of malloc() pool
  132. */
  133. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
  134. SZ_4K)
  135. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  136. - GENERATED_GBL_DATA_SIZE)
  137. #endif /* __AT91RM9200EK_CONFIG_H__ */