apf27.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. *
  4. * Configuration settings for the Armadeus Project motherboard APF27
  5. *
  6. * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <linux/stringify.h>
  11. #define CONFIG_ENV_VERSION 10
  12. #define CONFIG_BOARD_NAME apf27
  13. /*
  14. * SoC configurations
  15. */
  16. #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
  17. #define CONFIG_MACH_TYPE 1698 /* APF27 */
  18. /*
  19. * Enable the call to miscellaneous platform dependent initialization.
  20. */
  21. /*
  22. * SPL
  23. */
  24. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  25. #define CONFIG_SPL_MAX_SIZE 2048
  26. /* NAND boot config */
  27. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  28. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
  29. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  30. #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
  31. /*
  32. * BOOTP options
  33. */
  34. #define CONFIG_BOOTP_BOOTFILESIZE
  35. #define CONFIG_HOSTNAME "apf27"
  36. #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
  37. /*
  38. * Memory configurations
  39. */
  40. #define CONFIG_NR_DRAM_POPULATED 1
  41. #define ACFG_SDRAM_MBYTE_SYZE 64
  42. #define PHYS_SDRAM_1 0xA0000000
  43. #define PHYS_SDRAM_2 0xB0000000
  44. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  45. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
  46. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
  47. + PHYS_SDRAM_1_SIZE - 0x0100000)
  48. /*
  49. * FLASH organization
  50. */
  51. #define ACFG_MONITOR_OFFSET 0x00000000
  52. #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
  53. #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
  54. #define CONFIG_FIRMWARE_OFFSET 0x00200000
  55. #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
  56. #define CONFIG_KERNEL_OFFSET 0x00300000
  57. #define CONFIG_ROOTFS_OFFSET 0x00800000
  58. /*
  59. * U-Boot general configurations
  60. */
  61. #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
  62. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  63. /* Boot argument buffer size */
  64. /*
  65. * Boot Linux
  66. */
  67. #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
  68. #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
  69. #define CONFIG_INITRD_TAG /* send initrd params */
  70. #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
  71. #define ACFG_CONSOLE_DEV ttySMX0
  72. #define CONFIG_BOOTCOMMAND "run ubifsboot"
  73. #define CONFIG_SYS_AUTOLOAD "no"
  74. /*
  75. * Default load address for user programs and kernel
  76. */
  77. #define CONFIG_LOADADDR 0xA0000000
  78. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  79. /*
  80. * Extra Environments
  81. */
  82. #define CONFIG_EXTRA_ENV_SETTINGS \
  83. "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
  84. "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
  85. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  86. "partition=nand0,6\0" \
  87. "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
  88. "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
  89. "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
  90. "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
  91. "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
  92. "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
  93. "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
  94. "kernel_addr_r=A0000000\0" \
  95. "check_env=if test -n ${flash_env_version}; " \
  96. "then env default env_version; " \
  97. "else env set flash_env_version ${env_version}; env save; "\
  98. "fi; " \
  99. "if itest ${flash_env_version} < ${env_version}; then " \
  100. "echo \"*** Warning - Environment version" \
  101. " change suggests: run flash_reset_env; reset\"; "\
  102. "env default flash_reset_env; "\
  103. "fi; \0" \
  104. "check_flash=nand lock; nand unlock ${env_addr}; \0" \
  105. "flash_reset_env=env default -f -a; saveenv; run update_env;" \
  106. "echo Flash environment variables erased!\0" \
  107. "download_uboot=tftpboot ${loadaddr} ${board_name}" \
  108. "-u-boot-with-spl.bin\0" \
  109. "flash_uboot=nand unlock ${u-boot_addr} ;" \
  110. "nand erase.part u-boot;" \
  111. "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
  112. "then nand lock; nand unlock ${env_addr};" \
  113. "echo Flashing of uboot succeed;" \
  114. "else echo Flashing of uboot failed;" \
  115. "fi; \0" \
  116. "update_uboot=run download_uboot flash_uboot\0" \
  117. "download_env=tftpboot ${loadaddr} ${board_name}" \
  118. "-u-boot-env.txt\0" \
  119. "flash_env=env import -t ${loadaddr}; env save; \0" \
  120. "update_env=run download_env flash_env\0" \
  121. "update_all=run update_env update_uboot\0" \
  122. "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
  123. /*
  124. * Serial Driver
  125. */
  126. #define CONFIG_MXC_UART_BASE UART1_BASE
  127. /*
  128. * NOR
  129. */
  130. /*
  131. * NAND
  132. */
  133. #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
  134. #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
  135. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  136. #define CONFIG_MXC_NAND_HWECC
  137. #define CONFIG_SYS_NAND_LARGEPAGE
  138. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  139. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  140. #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
  141. CONFIG_SYS_NAND_PAGE_SIZE
  142. #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
  143. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
  144. #define NAND_MAX_CHIPS 1
  145. #define CONFIG_FLASH_SHOW_PROGRESS 45
  146. #define CONFIG_SYS_NAND_QUIET 1
  147. /*
  148. * Partitions & Filsystems
  149. */
  150. /*
  151. * Ethernet (on SOC imx FEC)
  152. */
  153. #define CONFIG_FEC_MXC
  154. #define CONFIG_FEC_MXC_PHYADDR 0x1f
  155. /*
  156. * FPGA
  157. */
  158. #define CONFIG_FPGA_COUNT 1
  159. #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
  160. #define CONFIG_SYS_FPGA_PROG_FEEDBACK
  161. #define CONFIG_SYS_FPGA_CHECK_CTRLC
  162. #define CONFIG_SYS_FPGA_CHECK_ERROR
  163. /*
  164. * Fuses - IIM
  165. */
  166. #ifdef CONFIG_CMD_IMX_FUSE
  167. #define IIM_MAC_BANK 0
  168. #define IIM_MAC_ROW 5
  169. #define IIM0_SCC_KEY 11
  170. #define IIM1_SUID 1
  171. #endif
  172. /*
  173. * I2C
  174. */
  175. #ifdef CONFIG_CMD_I2C
  176. #define CONFIG_SYS_I2C
  177. #define CONFIG_SYS_I2C_MXC
  178. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  179. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  180. #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
  181. #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
  182. #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
  183. #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
  184. #define CONFIG_SYS_I2C_NOPROBES { }
  185. #ifdef CONFIG_CMD_EEPROM
  186. # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
  187. # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  188. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  189. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
  190. #endif /* CONFIG_CMD_EEPROM */
  191. #endif /* CONFIG_CMD_I2C */
  192. /*
  193. * SD/MMC
  194. */
  195. #ifdef CONFIG_CMD_MMC
  196. #define CONFIG_MXC_MCI_REGS_BASE 0x10014000
  197. #endif
  198. /*
  199. * RTC
  200. */
  201. #ifdef CONFIG_CMD_DATE
  202. #define CONFIG_RTC_DS1374
  203. #define CONFIG_SYS_RTC_BUS_NUM 0
  204. #endif /* CONFIG_CMD_DATE */
  205. /*
  206. * PLL
  207. *
  208. * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
  209. * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
  210. */
  211. #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
  212. #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
  213. /* micron 64MB */
  214. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  215. #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
  216. #endif
  217. #if (ACFG_SDRAM_MBYTE_SYZE == 128)
  218. /* micron 128MB */
  219. #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
  220. #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
  221. #endif
  222. #if (ACFG_SDRAM_MBYTE_SYZE == 256)
  223. /* micron 256MB */
  224. #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
  225. #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
  226. #endif
  227. #endif /* __CONFIG_H */