amcore.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Sysam AMCORE board configuration
  4. *
  5. * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
  6. */
  7. #ifndef __AMCORE_CONFIG_H
  8. #define __AMCORE_CONFIG_H
  9. #define CONFIG_HOSTNAME "AMCORE"
  10. #define CONFIG_MCFTMR
  11. #define CONFIG_MCFUART
  12. #define CONFIG_SYS_UART_PORT 0
  13. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  14. #define CONFIG_BOOTCOMMAND "bootm ffc20000"
  15. #define CONFIG_EXTRA_ENV_SETTINGS \
  16. "upgrade_uboot=loady; " \
  17. "protect off 0xffc00000 0xffc1ffff; " \
  18. "erase 0xffc00000 0xffc1ffff; " \
  19. "cp.b 0x20000 0xffc00000 ${filesize}\0" \
  20. "upgrade_kernel=loady; " \
  21. "erase 0xffc20000 0xffefffff; " \
  22. "cp.b 0x20000 0xffc20000 ${filesize}\0" \
  23. "upgrade_jffs2=loady; " \
  24. "erase 0xfff00000 0xffffffff; " \
  25. "cp.b 0x20000 0xfff00000 ${filesize}\0"
  26. /* undef to save memory */
  27. #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
  28. #define CONFIG_SYS_HZ 1000
  29. #define CONFIG_SYS_CLK 45000000
  30. #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
  31. /* Register Base Addrs */
  32. #define CONFIG_SYS_MBAR 0x10000000
  33. /* Definitions for initial stack pointer and data area (in DPRAM) */
  34. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  35. /* size of internal SRAM */
  36. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  37. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  38. GENERATED_GBL_DATA_SIZE)
  39. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  40. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  41. #define CONFIG_SYS_SDRAM_SIZE 0x1000000
  42. #define CONFIG_SYS_FLASH_BASE 0xffc00000
  43. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  44. #define CONFIG_SYS_MAX_FLASH_SECT 1024
  45. #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
  46. /* amcore design has flash data bytes wired swapped */
  47. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  48. /* reserve 128-4KB */
  49. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  50. #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
  51. #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
  52. #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
  53. #define LDS_BOARD_TEXT \
  54. . = DEFINED(env_offset) ? env_offset : .; \
  55. env/embedded.o(.text*);
  56. /* memory map space for linux boot data */
  57. #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
  58. /*
  59. * Cache Configuration
  60. *
  61. * Special 8K version 3 core cache.
  62. * This is a single unified instruction/data cache.
  63. * sdram - single region - no masks
  64. */
  65. #define CONFIG_SYS_CACHELINE_SIZE 16
  66. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  67. CONFIG_SYS_INIT_RAM_SIZE - 8)
  68. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  69. CONFIG_SYS_INIT_RAM_SIZE - 4)
  70. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
  71. #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
  72. CF_ACR_EN)
  73. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
  74. CF_CACR_EC)
  75. /* CS0 - AMD Flash, address 0xffc00000 */
  76. #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
  77. /* 4MB, AA=0,V=1 C/I BIT for errata */
  78. #define CONFIG_SYS_CS0_MASK 0x003f0001
  79. /* WS=10, AA=1, PS=16bit (10) */
  80. #define CONFIG_SYS_CS0_CTRL 0x1980
  81. /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
  82. #define CONFIG_SYS_CS1_BASE 0x3000
  83. #define CONFIG_SYS_CS1_MASK 0x00070001
  84. #define CONFIG_SYS_CS1_CTRL 0x0100
  85. #endif /* __AMCORE_CONFIG_H */