adp-ag101p.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Andes Technology Corporation
  4. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  5. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <asm/arch-ag101/ag101.h>
  10. /*
  11. * CPU and Board Configuration Options
  12. */
  13. #define CONFIG_USE_INTERRUPT
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #define CONFIG_ARCH_MAP_SYSMEM
  16. #define CONFIG_BOOTP_SERVERIP
  17. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  18. #define CONFIG_MEM_REMAP
  19. #endif
  20. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  21. #ifdef CONFIG_OF_CONTROL
  22. #undef CONFIG_OF_SEPARATE
  23. #define CONFIG_OF_EMBED
  24. #endif
  25. #endif
  26. /*
  27. * Timer
  28. */
  29. #define CONFIG_SYS_CLK_FREQ 39062500
  30. #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
  31. /*
  32. * Use Externel CLOCK or PCLK
  33. */
  34. #undef CONFIG_FTRTC010_EXTCLK
  35. #ifndef CONFIG_FTRTC010_EXTCLK
  36. #define CONFIG_FTRTC010_PCLK
  37. #endif
  38. #ifdef CONFIG_FTRTC010_EXTCLK
  39. #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
  40. #else
  41. #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
  42. #endif
  43. #define TIMER_LOAD_VAL 0xffffffff
  44. /*
  45. * Real Time Clock
  46. */
  47. #define CONFIG_RTC_FTRTC010
  48. /*
  49. * Real Time Clock Divider
  50. * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
  51. */
  52. #define OSC_5MHZ (5*1000000)
  53. #define OSC_CLK (4*OSC_5MHZ)
  54. #define RTC_DIV_COUNT (0.5) /* Why?? */
  55. /*
  56. * Serial console configuration
  57. */
  58. /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  59. #define CONFIG_SYS_NS16550_SERIAL
  60. #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
  61. #ifndef CONFIG_DM_SERIAL
  62. #define CONFIG_SYS_NS16550_REG_SIZE -4
  63. #endif
  64. #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
  65. /*
  66. * Miscellaneous configurable options
  67. */
  68. /*
  69. * Size of malloc() pool
  70. */
  71. /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  72. #define CONFIG_SYS_MALLOC_LEN (512 << 10)
  73. /*
  74. * AHB Controller configuration
  75. */
  76. #define CONFIG_FTAHBC020S
  77. #ifdef CONFIG_FTAHBC020S
  78. #include <faraday/ftahbc020s.h>
  79. /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  80. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
  81. /*
  82. * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  83. * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  84. * in C language.
  85. */
  86. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
  87. (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
  88. FTAHBC020S_SLAVE_BSR_SIZE(0xb))
  89. #endif
  90. /*
  91. * Watchdog
  92. */
  93. #define CONFIG_FTWDT010_WATCHDOG
  94. /*
  95. * PMU Power controller configuration
  96. */
  97. #define CONFIG_PMU
  98. #define CONFIG_FTPMU010_POWER
  99. #ifdef CONFIG_FTPMU010_POWER
  100. #include <faraday/ftpmu010.h>
  101. #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
  102. #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
  103. FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
  104. FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
  105. FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
  106. FTPMU010_SDRAMHTC_CKE_DCSR | \
  107. FTPMU010_SDRAMHTC_DQM_DCSR | \
  108. FTPMU010_SDRAMHTC_SDCLK_DCSR)
  109. #endif
  110. /*
  111. * SDRAM controller configuration
  112. */
  113. #define CONFIG_FTSDMC021
  114. #ifdef CONFIG_FTSDMC021
  115. #include <faraday/ftsdmc021.h>
  116. #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
  117. FTSDMC021_TP1_TRP(1) | \
  118. FTSDMC021_TP1_TRCD(1) | \
  119. FTSDMC021_TP1_TRF(3) | \
  120. FTSDMC021_TP1_TWR(1) | \
  121. FTSDMC021_TP1_TCL(2))
  122. #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
  123. FTSDMC021_TP2_INI_REFT(8) | \
  124. FTSDMC021_TP2_REF_INTV(0x180))
  125. /*
  126. * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
  127. * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
  128. * C language.
  129. */
  130. #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
  131. FTSDMC021_CR1_DSZ(3) | \
  132. FTSDMC021_CR1_MBW(2) | \
  133. FTSDMC021_CR1_BNKSIZE(6))
  134. #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
  135. FTSDMC021_CR2_IREF | \
  136. FTSDMC021_CR2_ISMR)
  137. #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
  138. #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
  139. CONFIG_SYS_FTSDMC021_BANK0_BASE)
  140. #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
  141. (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
  142. #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
  143. CONFIG_SYS_FTSDMC021_BANK1_BASE)
  144. #endif
  145. /*
  146. * Physical Memory Map
  147. */
  148. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  149. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  150. #else
  151. #ifdef CONFIG_MEM_REMAP
  152. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  153. #else
  154. #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
  155. #endif
  156. #endif
  157. #define PHYS_SDRAM_1 \
  158. (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
  159. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  160. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  161. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  162. #else
  163. #ifdef CONFIG_MEM_REMAP
  164. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  165. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  166. #else
  167. #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
  168. #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
  169. #endif
  170. #endif
  171. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
  172. #ifdef CONFIG_MEM_REMAP
  173. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  174. GENERATED_GBL_DATA_SIZE)
  175. #else
  176. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
  177. GENERATED_GBL_DATA_SIZE)
  178. #endif /* CONFIG_MEM_REMAP */
  179. /*
  180. * Load address and memory test area should agree with
  181. * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
  182. */
  183. #define CONFIG_SYS_LOAD_ADDR 0x300000
  184. /* memtest works on 63 MB in DRAM */
  185. /*
  186. * Static memory controller configuration
  187. */
  188. #define CONFIG_FTSMC020
  189. #ifdef CONFIG_FTSMC020
  190. #include <faraday/ftsmc020.h>
  191. #define CONFIG_SYS_FTSMC020_CONFIGS { \
  192. { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
  193. { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
  194. }
  195. #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
  196. #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
  197. FTSMC020_BANK_SIZE_32M | \
  198. FTSMC020_BANK_MBW_32)
  199. #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
  200. FTSMC020_TPR_AST(1) | \
  201. FTSMC020_TPR_CTW(1) | \
  202. FTSMC020_TPR_ATI(1) | \
  203. FTSMC020_TPR_AT2(1) | \
  204. FTSMC020_TPR_WTC(1) | \
  205. FTSMC020_TPR_AHT(1) | \
  206. FTSMC020_TPR_TRNA(1))
  207. #endif
  208. /*
  209. * FLASH on ADP_AG101P is connected to BANK0
  210. * Just disalbe the other BANK to avoid detection error.
  211. */
  212. #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
  213. FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
  214. FTSMC020_BANK_SIZE_32M | \
  215. FTSMC020_BANK_MBW_32)
  216. #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
  217. FTSMC020_TPR_CTW(3) | \
  218. FTSMC020_TPR_ATI(0xf) | \
  219. FTSMC020_TPR_AT2(3) | \
  220. FTSMC020_TPR_WTC(3) | \
  221. FTSMC020_TPR_AHT(3) | \
  222. FTSMC020_TPR_TRNA(0xf))
  223. #define FTSMC020_BANK1_CONFIG (0x00)
  224. #define FTSMC020_BANK1_TIMING (0x00)
  225. #endif /* CONFIG_FTSMC020 */
  226. /*
  227. * FLASH and environment organization
  228. */
  229. /* use CFI framework */
  230. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  231. #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
  232. /* support JEDEC */
  233. /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
  234. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  235. #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
  236. #else
  237. #ifdef CONFIG_MEM_REMAP
  238. #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
  239. #else
  240. #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
  241. #endif
  242. #endif /* CONFIG_MEM_REMAP */
  243. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  244. #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
  245. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  246. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
  247. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
  248. /* max number of memory banks */
  249. /*
  250. * There are 4 banks supported for this Controller,
  251. * but we have only 1 bank connected to flash on board
  252. */
  253. #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
  254. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  255. #endif
  256. #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
  257. /* max number of sectors on one chip */
  258. #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
  259. #define CONFIG_SYS_MAX_FLASH_SECT 512
  260. /* environments */
  261. /*
  262. * For booting Linux, the board info and command line data
  263. * have to be in the first 16 MB of memory, since this is
  264. * the maximum mapped by the Linux kernel during initialization.
  265. */
  266. /* Initial Memory map for Linux*/
  267. #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
  268. /* Increase max gunzip size */
  269. #define CONFIG_SYS_BOOTM_LEN (64 << 20)
  270. #endif /* __CONFIG_H */