TQM834x.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2005
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * TQM8349 board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_E300 1 /* E300 Family */
  15. /* board pre init: do not call, nothing to do */
  16. /* detect the number of flash banks */
  17. /*
  18. * DDR Setup
  19. */
  20. /* DDR is system memory*/
  21. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  22. #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
  23. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  24. #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
  25. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  26. /*
  27. * FLASH on the Local Bus
  28. */
  29. #undef CONFIG_SYS_FLASH_CHECKSUM
  30. #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
  31. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
  32. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
  33. /*
  34. * FLASH bank number detection
  35. */
  36. /*
  37. * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
  38. * Flash banks has to be determined at runtime and stored in a gloabl variable
  39. * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
  40. * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
  41. * flash_info, and should be made sufficiently large to accomodate the number
  42. * of banks that might actually be detected. Since most (all?) Flash related
  43. * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
  44. * the board, it is defined as tqm834x_num_flash_banks.
  45. */
  46. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
  47. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
  48. /* disable remaining mappings */
  49. #define CONFIG_SYS_BR1_PRELIM 0x00000000
  50. #define CONFIG_SYS_OR1_PRELIM 0x00000000
  51. #define CONFIG_SYS_BR2_PRELIM 0x00000000
  52. #define CONFIG_SYS_OR2_PRELIM 0x00000000
  53. #define CONFIG_SYS_BR3_PRELIM 0x00000000
  54. #define CONFIG_SYS_OR3_PRELIM 0x00000000
  55. /*
  56. * Monitor config
  57. */
  58. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  59. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  60. # define CONFIG_SYS_RAMBOOT
  61. #else
  62. # undef CONFIG_SYS_RAMBOOT
  63. #endif
  64. #define CONFIG_SYS_INIT_RAM_LOCK 1
  65. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
  66. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  67. #define CONFIG_SYS_GBL_DATA_OFFSET \
  68. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  69. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  70. /* Reserve 384 kB = 3 sect. for Mon */
  71. #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
  72. /* Reserve 512 kB for malloc */
  73. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  74. /*
  75. * Serial Port
  76. */
  77. #define CONFIG_SYS_NS16550_SERIAL
  78. #define CONFIG_SYS_NS16550_REG_SIZE 1
  79. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  80. #define CONFIG_SYS_BAUDRATE_TABLE \
  81. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  82. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  83. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  84. /*
  85. * I2C
  86. */
  87. #define CONFIG_SYS_I2C
  88. #define CONFIG_SYS_I2C_FSL
  89. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  90. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  91. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  92. /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
  93. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
  94. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
  95. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
  96. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
  97. /* I2C RTC */
  98. #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
  99. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  100. /*
  101. * TSEC
  102. */
  103. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  104. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  105. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  106. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
  107. #if defined(CONFIG_TSEC_ENET)
  108. #define CONFIG_TSEC1 1
  109. #define CONFIG_TSEC1_NAME "TSEC0"
  110. #define CONFIG_TSEC2 1
  111. #define CONFIG_TSEC2_NAME "TSEC1"
  112. #define TSEC1_PHY_ADDR 2
  113. #define TSEC2_PHY_ADDR 1
  114. #define TSEC1_PHYIDX 0
  115. #define TSEC2_PHYIDX 0
  116. #define TSEC1_FLAGS TSEC_GIGABIT
  117. #define TSEC2_FLAGS TSEC_GIGABIT
  118. /* Options are: TSEC[0-1] */
  119. #define CONFIG_ETHPRIME "TSEC0"
  120. #endif /* CONFIG_TSEC_ENET */
  121. #if defined(CONFIG_PCI)
  122. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  123. /* PCI1 host bridge */
  124. #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
  125. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  126. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  127. #define CONFIG_SYS_PCI1_MMIO_BASE \
  128. (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
  129. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  130. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  131. #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
  132. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  133. #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
  134. #if !defined(CONFIG_PCI_PNP)
  135. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
  136. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
  137. #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
  138. #endif
  139. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  140. #endif /* CONFIG_PCI */
  141. /*
  142. * Environment
  143. */
  144. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  145. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  146. /*
  147. * BOOTP options
  148. */
  149. #define CONFIG_BOOTP_BOOTFILESIZE
  150. /*
  151. * Miscellaneous configurable options
  152. */
  153. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  154. #undef CONFIG_WATCHDOG /* watchdog disabled */
  155. /*
  156. * For booting Linux, the board info and command line data
  157. * have to be in the first 256 MB of memory, since this is
  158. * the maximum mapped by the Linux kernel during initialization.
  159. */
  160. /* Initial Memory map for Linux */
  161. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  162. /* System IO Config */
  163. #define CONFIG_SYS_SICRH 0
  164. #define CONFIG_SYS_SICRL SICRL_LDP_A
  165. /* PCI */
  166. #ifdef CONFIG_PCI
  167. #define CONFIG_PCI_INDIRECT_BRIDGE
  168. #endif
  169. #if defined(CONFIG_CMD_KGDB)
  170. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  171. #endif
  172. /*
  173. * Environment Configuration
  174. */
  175. /* default location for tftp and bootm */
  176. #define CONFIG_LOADADDR 400000
  177. #define CONFIG_EXTRA_ENV_SETTINGS \
  178. "netdev=eth0\0" \
  179. "hostname=tqm834x\0" \
  180. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  181. "nfsroot=${serverip}:${rootpath}\0" \
  182. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  183. "addip=setenv bootargs ${bootargs} " \
  184. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  185. ":${hostname}:${netdev}:off panic=1\0" \
  186. "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
  187. "flash_nfs_old=run nfsargs addip addcons;" \
  188. "bootm ${kernel_addr}\0" \
  189. "flash_nfs=run nfsargs addip addcons;" \
  190. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  191. "flash_self_old=run ramargs addip addcons;" \
  192. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  193. "flash_self=run ramargs addip addcons;" \
  194. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  195. "net_nfs_old=tftp 400000 ${bootfile};" \
  196. "run nfsargs addip addcons;bootm\0" \
  197. "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
  198. "tftp ${fdt_addr_r} ${fdt_file}; " \
  199. "run nfsargs addip addcons; " \
  200. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  201. "rootpath=/opt/eldk/ppc_6xx\0" \
  202. "bootfile=tqm834x/uImage\0" \
  203. "fdtfile=tqm834x/tqm834x.dtb\0" \
  204. "kernel_addr_r=400000\0" \
  205. "fdt_addr_r=600000\0" \
  206. "ramdisk_addr_r=800000\0" \
  207. "kernel_addr=800C0000\0" \
  208. "fdt_addr=800A0000\0" \
  209. "ramdisk_addr=80300000\0" \
  210. "u-boot=tqm834x/u-boot.bin\0" \
  211. "load=tftp 200000 ${u-boot}\0" \
  212. "update=protect off 80000000 +${filesize};" \
  213. "era 80000000 +${filesize};" \
  214. "cp.b 200000 80000000 ${filesize}\0" \
  215. "upd=run load update\0" \
  216. ""
  217. #define CONFIG_BOOTCOMMAND "run flash_self"
  218. /*
  219. * JFFS2 partitions
  220. */
  221. /* mtdparts command line support */
  222. /* default mtd partition table */
  223. #endif /* __CONFIG_H */