T4240RDB.h 21 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * T4240 RDB board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_FSL_SATA_V2
  13. #define CONFIG_PCIE4
  14. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  15. #ifdef CONFIG_RAMBOOT_PBL
  16. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  17. #ifndef CONFIG_SDCARD
  18. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  19. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  20. #else
  21. #define CONFIG_SPL_FLUSH_IMAGE
  22. #define CONFIG_SPL_PAD_TO 0x40000
  23. #define CONFIG_SPL_MAX_SIZE 0x28000
  24. #define RESET_VECTOR_OFFSET 0x27FFC
  25. #define BOOT_PAGE_OFFSET 0x27000
  26. #ifdef CONFIG_SDCARD
  27. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  28. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  29. #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
  30. #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
  31. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  32. #ifndef CONFIG_SPL_BUILD
  33. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  34. #endif
  35. #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  36. #endif
  37. #ifdef CONFIG_SPL_BUILD
  38. #define CONFIG_SPL_SKIP_RELOCATE
  39. #define CONFIG_SPL_COMMON_INIT_DDR
  40. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41. #endif
  42. #endif
  43. #endif /* CONFIG_RAMBOOT_PBL */
  44. #define CONFIG_DDR_ECC
  45. /* High Level Configuration Options */
  46. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  47. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  48. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  49. #endif
  50. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  51. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  52. #define CONFIG_PCIE1 /* PCIE controller 1 */
  53. #define CONFIG_PCIE2 /* PCIE controller 2 */
  54. #define CONFIG_PCIE3 /* PCIE controller 3 */
  55. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  56. /*
  57. * These can be toggled for performance analysis, otherwise use default.
  58. */
  59. #define CONFIG_SYS_CACHE_STASHING
  60. #define CONFIG_BTB /* toggle branch predition */
  61. #ifdef CONFIG_DDR_ECC
  62. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  63. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  64. #endif
  65. #define CONFIG_ENABLE_36BIT_PHYS
  66. /*
  67. * Config the L3 Cache as L3 SRAM
  68. */
  69. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  70. #define CONFIG_SYS_L3_SIZE (512 << 10)
  71. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  72. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  73. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  74. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  75. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  76. #define CONFIG_SYS_DCSRBAR 0xf0000000
  77. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  78. /*
  79. * DDR Setup
  80. */
  81. #define CONFIG_VERY_BIG_RAM
  82. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  83. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  84. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  85. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  86. #define CONFIG_DDR_SPD
  87. /*
  88. * IFC Definitions
  89. */
  90. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  91. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  92. #ifdef CONFIG_SPL_BUILD
  93. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  94. #else
  95. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  96. #endif
  97. #define CONFIG_HWCONFIG
  98. /* define to use L1 as initial stack */
  99. #define CONFIG_L1_INIT_RAM
  100. #define CONFIG_SYS_INIT_RAM_LOCK
  101. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  102. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  103. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  104. /* The assembler doesn't like typecast */
  105. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  106. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  107. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  108. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  109. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  110. GENERATED_GBL_DATA_SIZE)
  111. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  112. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  113. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  114. /* Serial Port - controlled on board with jumper J8
  115. * open - index 2
  116. * shorted - index 1
  117. */
  118. #define CONFIG_SYS_NS16550_SERIAL
  119. #define CONFIG_SYS_NS16550_REG_SIZE 1
  120. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  121. #define CONFIG_SYS_BAUDRATE_TABLE \
  122. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  123. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  124. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  125. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  126. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  127. /* I2C */
  128. #ifndef CONFIG_DM_I2C
  129. #define CONFIG_SYS_I2C
  130. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  131. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  132. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  133. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  134. #else
  135. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  136. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  137. #endif
  138. #define CONFIG_SYS_I2C_FSL
  139. /*
  140. * General PCI
  141. * Memory space is mapped 1-1, but I/O space must start from 0.
  142. */
  143. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  144. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  145. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  146. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  147. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  148. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  149. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  150. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  151. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  152. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  153. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  154. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  155. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  156. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  157. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  158. /* controller 4, Base address 203000 */
  159. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  160. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  161. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  162. #ifdef CONFIG_PCI
  163. #if !defined(CONFIG_DM_PCI)
  164. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  165. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  166. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  167. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  168. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  169. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  170. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  171. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  172. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  173. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  174. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  175. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  176. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  177. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  178. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  179. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  180. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  181. #define CONFIG_PCI_INDIRECT_BRIDGE
  182. #endif
  183. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  184. #endif /* CONFIG_PCI */
  185. /* SATA */
  186. #ifdef CONFIG_FSL_SATA_V2
  187. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  188. #define CONFIG_SATA1
  189. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  190. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  191. #define CONFIG_SATA2
  192. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  193. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  194. #define CONFIG_LBA48
  195. #endif
  196. #ifdef CONFIG_FMAN_ENET
  197. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  198. #endif
  199. /*
  200. * Environment
  201. */
  202. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  203. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  204. /*
  205. * Miscellaneous configurable options
  206. */
  207. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  208. /*
  209. * For booting Linux, the board info and command line data
  210. * have to be in the first 64 MB of memory, since this is
  211. * the maximum mapped by the Linux kernel during initialization.
  212. */
  213. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  214. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  215. #ifdef CONFIG_CMD_KGDB
  216. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  217. #endif
  218. /*
  219. * Environment Configuration
  220. */
  221. #define CONFIG_ROOTPATH "/opt/nfsroot"
  222. #define CONFIG_BOOTFILE "uImage"
  223. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  224. /* default location for tftp and bootm */
  225. #define CONFIG_LOADADDR 1000000
  226. #define CONFIG_HVBOOT \
  227. "setenv bootargs config-addr=0x60000000; " \
  228. "bootm 0x01000000 - 0x00f00000"
  229. #define CONFIG_SYS_CLK_FREQ 66666666
  230. #define CONFIG_DDR_CLK_FREQ 133333333
  231. #ifndef __ASSEMBLY__
  232. unsigned long get_board_sys_clk(void);
  233. unsigned long get_board_ddr_clk(void);
  234. #endif
  235. /*
  236. * DDR Setup
  237. */
  238. #define CONFIG_SYS_SPD_BUS_NUM 0
  239. #define SPD_EEPROM_ADDRESS1 0x52
  240. #define SPD_EEPROM_ADDRESS2 0x54
  241. #define SPD_EEPROM_ADDRESS3 0x56
  242. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  243. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  244. /*
  245. * IFC Definitions
  246. */
  247. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  248. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  249. + 0x8000000) | \
  250. CSPR_PORT_SIZE_16 | \
  251. CSPR_MSEL_NOR | \
  252. CSPR_V)
  253. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  254. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  255. CSPR_PORT_SIZE_16 | \
  256. CSPR_MSEL_NOR | \
  257. CSPR_V)
  258. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  259. /* NOR Flash Timing Params */
  260. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  261. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  262. FTIM0_NOR_TEADC(0x5) | \
  263. FTIM0_NOR_TEAHC(0x5))
  264. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  265. FTIM1_NOR_TRAD_NOR(0x1A) |\
  266. FTIM1_NOR_TSEQRAD_NOR(0x13))
  267. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  268. FTIM2_NOR_TCH(0x4) | \
  269. FTIM2_NOR_TWPH(0x0E) | \
  270. FTIM2_NOR_TWP(0x1c))
  271. #define CONFIG_SYS_NOR_FTIM3 0x0
  272. #define CONFIG_SYS_FLASH_QUIET_TEST
  273. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  274. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  275. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  276. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  277. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  278. #define CONFIG_SYS_FLASH_EMPTY_INFO
  279. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  280. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  281. /* NAND Flash on IFC */
  282. #define CONFIG_NAND_FSL_IFC
  283. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  284. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  285. #define CONFIG_SYS_NAND_BASE 0xff800000
  286. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  287. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  288. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  289. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  290. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  291. | CSPR_V)
  292. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  293. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  294. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  295. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  296. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  297. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  298. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  299. | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
  300. #define CONFIG_SYS_NAND_ONFI_DETECTION
  301. /* ONFI NAND Flash mode0 Timing Params */
  302. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  303. FTIM0_NAND_TWP(0x18) | \
  304. FTIM0_NAND_TWCHT(0x07) | \
  305. FTIM0_NAND_TWH(0x0a))
  306. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  307. FTIM1_NAND_TWBE(0x39) | \
  308. FTIM1_NAND_TRR(0x0e) | \
  309. FTIM1_NAND_TRP(0x18))
  310. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  311. FTIM2_NAND_TREH(0x0a) | \
  312. FTIM2_NAND_TWHRE(0x1e))
  313. #define CONFIG_SYS_NAND_FTIM3 0x0
  314. #define CONFIG_SYS_NAND_DDR_LAW 11
  315. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  316. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  317. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  318. #if defined(CONFIG_MTD_RAW_NAND)
  319. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  320. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  321. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  322. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  323. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  324. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  325. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  326. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  327. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  328. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  329. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  330. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  331. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  332. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  333. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  334. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  335. #else
  336. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  337. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  338. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  339. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  340. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  341. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  342. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  343. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  344. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  345. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  346. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  347. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  348. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  349. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  350. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  351. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  352. #endif
  353. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  354. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  355. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  356. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  357. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  358. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  359. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  360. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  361. /* CPLD on IFC */
  362. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  363. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  364. #define CONFIG_SYS_CSPR3_EXT (0xf)
  365. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  366. | CSPR_PORT_SIZE_8 \
  367. | CSPR_MSEL_GPCM \
  368. | CSPR_V)
  369. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  370. #define CONFIG_SYS_CSOR3 0x0
  371. /* CPLD Timing parameters for IFC CS3 */
  372. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  373. FTIM0_GPCM_TEADC(0x0e) | \
  374. FTIM0_GPCM_TEAHC(0x0e))
  375. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  376. FTIM1_GPCM_TRAD(0x1f))
  377. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  378. FTIM2_GPCM_TCH(0x8) | \
  379. FTIM2_GPCM_TWP(0x1f))
  380. #define CONFIG_SYS_CS3_FTIM3 0x0
  381. #if defined(CONFIG_RAMBOOT_PBL)
  382. #define CONFIG_SYS_RAMBOOT
  383. #endif
  384. /* I2C */
  385. #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
  386. #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
  387. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  388. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
  389. #define I2C_MUX_CH_DEFAULT 0x8
  390. #define I2C_MUX_CH_VOL_MONITOR 0xa
  391. #define I2C_MUX_CH_VSC3316_FS 0xc
  392. #define I2C_MUX_CH_VSC3316_BS 0xd
  393. /* Voltage monitor on channel 2*/
  394. #define I2C_VOL_MONITOR_ADDR 0x40
  395. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  396. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  397. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  398. #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
  399. #ifndef CONFIG_SPL_BUILD
  400. #define CONFIG_VID
  401. #endif
  402. #define CONFIG_VOL_MONITOR_IR36021_SET
  403. #define CONFIG_VOL_MONITOR_IR36021_READ
  404. /* The lowest and highest voltage allowed for T4240RDB */
  405. #define VDD_MV_MIN 819
  406. #define VDD_MV_MAX 1212
  407. /*
  408. * eSPI - Enhanced SPI
  409. */
  410. /* Qman/Bman */
  411. #ifndef CONFIG_NOBQFMAN
  412. #define CONFIG_SYS_BMAN_NUM_PORTALS 50
  413. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  414. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  415. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  416. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  417. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  418. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  419. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  420. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  421. CONFIG_SYS_BMAN_CENA_SIZE)
  422. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  423. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  424. #define CONFIG_SYS_QMAN_NUM_PORTALS 50
  425. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  426. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  427. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  428. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  429. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  430. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  431. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  432. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  433. CONFIG_SYS_QMAN_CENA_SIZE)
  434. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  435. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  436. #define CONFIG_SYS_DPAA_FMAN
  437. #define CONFIG_SYS_DPAA_PME
  438. #define CONFIG_SYS_PMAN
  439. #define CONFIG_SYS_DPAA_DCE
  440. #define CONFIG_SYS_DPAA_RMAN
  441. #define CONFIG_SYS_INTERLAKEN
  442. /* Default address of microcode for the Linux Fman driver */
  443. #if defined(CONFIG_SPIFLASH)
  444. /*
  445. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  446. * env, so we got 0x110000.
  447. */
  448. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  449. #elif defined(CONFIG_SDCARD)
  450. /*
  451. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  452. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  453. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  454. */
  455. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  456. #elif defined(CONFIG_MTD_RAW_NAND)
  457. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  458. #else
  459. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  460. #endif
  461. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  462. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  463. #endif /* CONFIG_NOBQFMAN */
  464. #ifdef CONFIG_SYS_DPAA_FMAN
  465. #define CONFIG_CORTINA_FW_ADDR 0xefe00000
  466. #define CONFIG_CORTINA_FW_LENGTH 0x40000
  467. #define SGMII_PHY_ADDR1 0x0
  468. #define SGMII_PHY_ADDR2 0x1
  469. #define SGMII_PHY_ADDR3 0x2
  470. #define SGMII_PHY_ADDR4 0x3
  471. #define SGMII_PHY_ADDR5 0x4
  472. #define SGMII_PHY_ADDR6 0x5
  473. #define SGMII_PHY_ADDR7 0x6
  474. #define SGMII_PHY_ADDR8 0x7
  475. #define FM1_10GEC1_PHY_ADDR 0x10
  476. #define FM1_10GEC2_PHY_ADDR 0x11
  477. #define FM2_10GEC1_PHY_ADDR 0x12
  478. #define FM2_10GEC2_PHY_ADDR 0x13
  479. #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
  480. #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
  481. #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
  482. #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
  483. #endif
  484. /* SATA */
  485. #ifdef CONFIG_FSL_SATA_V2
  486. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  487. #define CONFIG_SATA1
  488. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  489. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  490. #define CONFIG_SATA2
  491. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  492. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  493. #define CONFIG_LBA48
  494. #endif
  495. #ifdef CONFIG_FMAN_ENET
  496. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  497. #endif
  498. /*
  499. * USB
  500. */
  501. #define CONFIG_USB_EHCI_FSL
  502. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  503. #define CONFIG_HAS_FSL_DR_USB
  504. #ifdef CONFIG_MMC
  505. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  506. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  507. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  508. #endif
  509. #define __USB_PHY_TYPE utmi
  510. /*
  511. * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
  512. * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
  513. * interleaving. It can be cacheline, page, bank, superbank.
  514. * See doc/README.fsl-ddr for details.
  515. */
  516. #ifdef CONFIG_ARCH_T4240
  517. #define CTRL_INTLV_PREFERED 3way_4KB
  518. #else
  519. #define CTRL_INTLV_PREFERED cacheline
  520. #endif
  521. #define CONFIG_EXTRA_ENV_SETTINGS \
  522. "hwconfig=fsl_ddr:" \
  523. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  524. "bank_intlv=auto;" \
  525. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  526. "netdev=eth0\0" \
  527. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  528. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  529. "tftpflash=tftpboot $loadaddr $uboot && " \
  530. "protect off $ubootaddr +$filesize && " \
  531. "erase $ubootaddr +$filesize && " \
  532. "cp.b $loadaddr $ubootaddr $filesize && " \
  533. "protect on $ubootaddr +$filesize && " \
  534. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  535. "consoledev=ttyS0\0" \
  536. "ramdiskaddr=2000000\0" \
  537. "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
  538. "fdtaddr=1e00000\0" \
  539. "fdtfile=t4240rdb/t4240rdb.dtb\0" \
  540. "bdev=sda3\0"
  541. #define CONFIG_HVBOOT \
  542. "setenv bootargs config-addr=0x60000000; " \
  543. "bootm 0x01000000 - 0x00f00000"
  544. #define CONFIG_LINUX \
  545. "setenv bootargs root=/dev/ram rw " \
  546. "console=$consoledev,$baudrate $othbootargs;" \
  547. "setenv ramdiskaddr 0x02000000;" \
  548. "setenv fdtaddr 0x00c00000;" \
  549. "setenv loadaddr 0x1000000;" \
  550. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  551. #define CONFIG_HDBOOT \
  552. "setenv bootargs root=/dev/$bdev rw " \
  553. "console=$consoledev,$baudrate $othbootargs;" \
  554. "tftp $loadaddr $bootfile;" \
  555. "tftp $fdtaddr $fdtfile;" \
  556. "bootm $loadaddr - $fdtaddr"
  557. #define CONFIG_NFSBOOTCOMMAND \
  558. "setenv bootargs root=/dev/nfs rw " \
  559. "nfsroot=$serverip:$rootpath " \
  560. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  561. "console=$consoledev,$baudrate $othbootargs;" \
  562. "tftp $loadaddr $bootfile;" \
  563. "tftp $fdtaddr $fdtfile;" \
  564. "bootm $loadaddr - $fdtaddr"
  565. #define CONFIG_RAMBOOTCOMMAND \
  566. "setenv bootargs root=/dev/ram rw " \
  567. "console=$consoledev,$baudrate $othbootargs;" \
  568. "tftp $ramdiskaddr $ramdiskfile;" \
  569. "tftp $loadaddr $bootfile;" \
  570. "tftp $fdtaddr $fdtfile;" \
  571. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  572. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  573. #include <asm/fsl_secure_boot.h>
  574. #endif /* __CONFIG_H */