T208xRDB.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * T2080 RDB/PCIe board configuration file
  8. */
  9. #ifndef __T2080RDB_H
  10. #define __T2080RDB_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #define CONFIG_FSL_SATA_V2
  14. /* High Level Configuration Options */
  15. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  16. #define CONFIG_ENABLE_36BIT_PHYS
  17. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  18. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  19. #ifdef CONFIG_RAMBOOT_PBL
  20. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  21. #define CONFIG_SPL_FLUSH_IMAGE
  22. #define CONFIG_SPL_PAD_TO 0x40000
  23. #define CONFIG_SPL_MAX_SIZE 0x28000
  24. #define RESET_VECTOR_OFFSET 0x27FFC
  25. #define BOOT_PAGE_OFFSET 0x27000
  26. #ifdef CONFIG_SPL_BUILD
  27. #define CONFIG_SPL_SKIP_RELOCATE
  28. #define CONFIG_SPL_COMMON_INIT_DDR
  29. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  30. #endif
  31. #ifdef CONFIG_MTD_RAW_NAND
  32. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  33. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  34. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  35. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  36. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  37. #endif
  38. #ifdef CONFIG_SPIFLASH
  39. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  40. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  41. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  42. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  43. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  44. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  45. #ifndef CONFIG_SPL_BUILD
  46. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  47. #endif
  48. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  49. #endif
  50. #ifdef CONFIG_SDCARD
  51. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  52. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  53. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  54. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  55. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  56. #ifndef CONFIG_SPL_BUILD
  57. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  58. #endif
  59. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  60. #endif
  61. #endif /* CONFIG_RAMBOOT_PBL */
  62. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  63. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  64. /* Set 1M boot space */
  65. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  66. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  67. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  68. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  69. #endif
  70. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  71. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  72. #endif
  73. /*
  74. * These can be toggled for performance analysis, otherwise use default.
  75. */
  76. #define CONFIG_SYS_CACHE_STASHING
  77. #define CONFIG_BTB /* toggle branch predition */
  78. #define CONFIG_DDR_ECC
  79. #ifdef CONFIG_DDR_ECC
  80. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  81. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  82. #endif
  83. #ifndef __ASSEMBLY__
  84. unsigned long get_board_sys_clk(void);
  85. unsigned long get_board_ddr_clk(void);
  86. #endif
  87. #define CONFIG_SYS_CLK_FREQ 66660000
  88. #define CONFIG_DDR_CLK_FREQ 133330000
  89. /*
  90. * Config the L3 Cache as L3 SRAM
  91. */
  92. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  93. #define CONFIG_SYS_L3_SIZE (512 << 10)
  94. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  95. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  96. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  97. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  98. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  99. #define CONFIG_SYS_DCSRBAR 0xf0000000
  100. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  101. /* EEPROM */
  102. #define CONFIG_ID_EEPROM
  103. #define CONFIG_SYS_I2C_EEPROM_NXID
  104. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  105. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  106. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  107. /*
  108. * DDR Setup
  109. */
  110. #define CONFIG_VERY_BIG_RAM
  111. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  112. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  113. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  114. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  115. #define CONFIG_DDR_SPD
  116. #define CONFIG_SYS_SPD_BUS_NUM 0
  117. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  118. #define SPD_EEPROM_ADDRESS1 0x51
  119. #define SPD_EEPROM_ADDRESS2 0x52
  120. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  121. #define CTRL_INTLV_PREFERED cacheline
  122. /*
  123. * IFC Definitions
  124. */
  125. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  126. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  127. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  128. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  129. CSPR_PORT_SIZE_16 | \
  130. CSPR_MSEL_NOR | \
  131. CSPR_V)
  132. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  133. /* NOR Flash Timing Params */
  134. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  135. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  136. FTIM0_NOR_TEADC(0x5) | \
  137. FTIM0_NOR_TEAHC(0x5))
  138. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  139. FTIM1_NOR_TRAD_NOR(0x1A) |\
  140. FTIM1_NOR_TSEQRAD_NOR(0x13))
  141. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  142. FTIM2_NOR_TCH(0x4) | \
  143. FTIM2_NOR_TWPH(0x0E) | \
  144. FTIM2_NOR_TWP(0x1c))
  145. #define CONFIG_SYS_NOR_FTIM3 0x0
  146. #define CONFIG_SYS_FLASH_QUIET_TEST
  147. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  148. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  149. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  150. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  151. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  152. #define CONFIG_SYS_FLASH_EMPTY_INFO
  153. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
  154. /* CPLD on IFC */
  155. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  156. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  157. #define CONFIG_SYS_CSPR2_EXT (0xf)
  158. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  159. | CSPR_PORT_SIZE_8 \
  160. | CSPR_MSEL_GPCM \
  161. | CSPR_V)
  162. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  163. #define CONFIG_SYS_CSOR2 0x0
  164. /* CPLD Timing parameters for IFC CS2 */
  165. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  166. FTIM0_GPCM_TEADC(0x0e) | \
  167. FTIM0_GPCM_TEAHC(0x0e))
  168. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  169. FTIM1_GPCM_TRAD(0x1f))
  170. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  171. FTIM2_GPCM_TCH(0x8) | \
  172. FTIM2_GPCM_TWP(0x1f))
  173. #define CONFIG_SYS_CS2_FTIM3 0x0
  174. /* NAND Flash on IFC */
  175. #define CONFIG_NAND_FSL_IFC
  176. #define CONFIG_SYS_NAND_BASE 0xff800000
  177. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  178. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  179. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  180. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  181. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  182. | CSPR_V)
  183. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  184. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  185. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  186. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  187. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  188. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  189. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  190. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  191. #define CONFIG_SYS_NAND_ONFI_DETECTION
  192. /* ONFI NAND Flash mode0 Timing Params */
  193. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  194. FTIM0_NAND_TWP(0x18) | \
  195. FTIM0_NAND_TWCHT(0x07) | \
  196. FTIM0_NAND_TWH(0x0a))
  197. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  198. FTIM1_NAND_TWBE(0x39) | \
  199. FTIM1_NAND_TRR(0x0e) | \
  200. FTIM1_NAND_TRP(0x18))
  201. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  202. FTIM2_NAND_TREH(0x0a) | \
  203. FTIM2_NAND_TWHRE(0x1e))
  204. #define CONFIG_SYS_NAND_FTIM3 0x0
  205. #define CONFIG_SYS_NAND_DDR_LAW 11
  206. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  207. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  208. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  209. #if defined(CONFIG_MTD_RAW_NAND)
  210. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  211. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  212. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  213. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  214. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  215. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  216. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  217. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  218. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  219. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  220. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  221. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  222. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  223. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  224. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  225. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  226. #else
  227. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  228. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  229. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  230. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  231. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  232. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  233. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  234. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  235. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  236. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  237. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  238. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  239. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  240. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  241. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  242. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  243. #endif
  244. #if defined(CONFIG_RAMBOOT_PBL)
  245. #define CONFIG_SYS_RAMBOOT
  246. #endif
  247. #ifdef CONFIG_SPL_BUILD
  248. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  249. #else
  250. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  251. #endif
  252. #define CONFIG_HWCONFIG
  253. /* define to use L1 as initial stack */
  254. #define CONFIG_L1_INIT_RAM
  255. #define CONFIG_SYS_INIT_RAM_LOCK
  256. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  257. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  258. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  259. /* The assembler doesn't like typecast */
  260. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  261. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  262. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  263. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  264. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  265. GENERATED_GBL_DATA_SIZE)
  266. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  267. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  268. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  269. /*
  270. * Serial Port
  271. */
  272. #define CONFIG_SYS_NS16550_SERIAL
  273. #define CONFIG_SYS_NS16550_REG_SIZE 1
  274. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  275. #define CONFIG_SYS_BAUDRATE_TABLE \
  276. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  277. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  278. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  279. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  280. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  281. /*
  282. * I2C
  283. */
  284. #ifndef CONFIG_DM_I2C
  285. #define CONFIG_SYS_I2C
  286. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  287. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  288. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  289. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  290. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  291. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  292. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  293. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  294. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  295. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  296. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  297. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  298. #else
  299. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  300. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  301. #endif
  302. #define CONFIG_SYS_I2C_FSL
  303. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  304. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  305. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  306. #define I2C_MUX_CH_DEFAULT 0x8
  307. #define I2C_MUX_CH_VOL_MONITOR 0xa
  308. #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
  309. #ifndef CONFIG_SPL_BUILD
  310. #define CONFIG_VID
  311. #endif
  312. #define CONFIG_VOL_MONITOR_IR36021_SET
  313. #define CONFIG_VOL_MONITOR_IR36021_READ
  314. /* The lowest and highest voltage allowed for T208xRDB */
  315. #define VDD_MV_MIN 819
  316. #define VDD_MV_MAX 1212
  317. /*
  318. * RapidIO
  319. */
  320. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  321. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  322. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  323. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  324. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  325. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  326. /*
  327. * for slave u-boot IMAGE instored in master memory space,
  328. * PHYS must be aligned based on the SIZE
  329. */
  330. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  331. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  332. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  333. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  334. /*
  335. * for slave UCODE and ENV instored in master memory space,
  336. * PHYS must be aligned based on the SIZE
  337. */
  338. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  339. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  340. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  341. /* slave core release by master*/
  342. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  343. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  344. /*
  345. * SRIO_PCIE_BOOT - SLAVE
  346. */
  347. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  348. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  349. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  350. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  351. #endif
  352. /*
  353. * eSPI - Enhanced SPI
  354. */
  355. /*
  356. * General PCI
  357. * Memory space is mapped 1-1, but I/O space must start from 0.
  358. */
  359. #define CONFIG_PCIE1 /* PCIE controller 1 */
  360. #define CONFIG_PCIE2 /* PCIE controller 2 */
  361. #define CONFIG_PCIE3 /* PCIE controller 3 */
  362. #define CONFIG_PCIE4 /* PCIE controller 4 */
  363. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  364. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  365. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  366. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  367. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  368. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  369. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  370. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  371. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  372. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  373. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  374. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  375. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  376. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  377. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  378. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  379. /* controller 4, Base address 203000 */
  380. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  381. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  382. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  383. #ifdef CONFIG_PCI
  384. #if !defined(CONFIG_DM_PCI)
  385. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  386. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  387. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  388. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  389. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  390. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  391. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  392. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  393. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  394. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  395. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  396. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  397. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  398. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  399. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  400. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  401. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  402. #define CONFIG_PCI_INDIRECT_BRIDGE
  403. #endif
  404. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  405. #endif
  406. /* Qman/Bman */
  407. #ifndef CONFIG_NOBQFMAN
  408. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  409. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  410. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  411. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  412. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  413. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  414. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  415. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  416. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  417. CONFIG_SYS_BMAN_CENA_SIZE)
  418. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  419. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  420. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  421. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  422. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  423. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  424. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  425. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  426. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  427. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  428. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  429. CONFIG_SYS_QMAN_CENA_SIZE)
  430. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  431. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  432. #define CONFIG_SYS_DPAA_FMAN
  433. #define CONFIG_SYS_DPAA_PME
  434. #define CONFIG_SYS_PMAN
  435. #define CONFIG_SYS_DPAA_DCE
  436. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  437. #define CONFIG_SYS_INTERLAKEN
  438. /* Default address of microcode for the Linux Fman driver */
  439. #if defined(CONFIG_SPIFLASH)
  440. /*
  441. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  442. * env, so we got 0x110000.
  443. */
  444. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  445. #define CONFIG_CORTINA_FW_ADDR 0x120000
  446. #elif defined(CONFIG_SDCARD)
  447. /*
  448. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  449. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  450. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  451. */
  452. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  453. #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
  454. #elif defined(CONFIG_MTD_RAW_NAND)
  455. #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  456. #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  457. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  458. /*
  459. * Slave has no ucode locally, it can fetch this from remote. When implementing
  460. * in two corenet boards, slave's ucode could be stored in master's memory
  461. * space, the address can be mapped from slave TLB->slave LAW->
  462. * slave SRIO or PCIE outbound window->master inbound window->
  463. * master LAW->the ucode address in master's memory space.
  464. */
  465. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  466. #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
  467. #else
  468. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  469. #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
  470. #endif
  471. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  472. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  473. #endif /* CONFIG_NOBQFMAN */
  474. #ifdef CONFIG_SYS_DPAA_FMAN
  475. #define CONFIG_CORTINA_FW_LENGTH 0x40000
  476. #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
  477. #define RGMII_PHY2_ADDR 0x02
  478. #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
  479. #define CORTINA_PHY_ADDR2 0x0d
  480. #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
  481. #define FM1_10GEC4_PHY_ADDR 0x01
  482. #endif
  483. #ifdef CONFIG_FMAN_ENET
  484. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  485. #endif
  486. /*
  487. * SATA
  488. */
  489. #ifdef CONFIG_FSL_SATA_V2
  490. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  491. #define CONFIG_SATA1
  492. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  493. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  494. #define CONFIG_SATA2
  495. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  496. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  497. #define CONFIG_LBA48
  498. #endif
  499. /*
  500. * USB
  501. */
  502. #ifdef CONFIG_USB_EHCI_HCD
  503. #define CONFIG_USB_EHCI_FSL
  504. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  505. #define CONFIG_HAS_FSL_DR_USB
  506. #endif
  507. /*
  508. * SDHC
  509. */
  510. #ifdef CONFIG_MMC
  511. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  512. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  513. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  514. #endif
  515. /*
  516. * Dynamic MTD Partition support with mtdparts
  517. */
  518. /*
  519. * Environment
  520. */
  521. /*
  522. * Miscellaneous configurable options
  523. */
  524. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  525. /*
  526. * For booting Linux, the board info and command line data
  527. * have to be in the first 64 MB of memory, since this is
  528. * the maximum mapped by the Linux kernel during initialization.
  529. */
  530. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  531. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  532. #ifdef CONFIG_CMD_KGDB
  533. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  534. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  535. #endif
  536. /*
  537. * Environment Configuration
  538. */
  539. #define CONFIG_ROOTPATH "/opt/nfsroot"
  540. #define CONFIG_BOOTFILE "uImage"
  541. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  542. /* default location for tftp and bootm */
  543. #define CONFIG_LOADADDR 1000000
  544. #define __USB_PHY_TYPE utmi
  545. #define CONFIG_EXTRA_ENV_SETTINGS \
  546. "hwconfig=fsl_ddr:" \
  547. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  548. "bank_intlv=auto;" \
  549. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  550. "netdev=eth0\0" \
  551. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  552. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  553. "tftpflash=tftpboot $loadaddr $uboot && " \
  554. "protect off $ubootaddr +$filesize && " \
  555. "erase $ubootaddr +$filesize && " \
  556. "cp.b $loadaddr $ubootaddr $filesize && " \
  557. "protect on $ubootaddr +$filesize && " \
  558. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  559. "consoledev=ttyS0\0" \
  560. "ramdiskaddr=2000000\0" \
  561. "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
  562. "fdtaddr=1e00000\0" \
  563. "fdtfile=t2080rdb/t2080rdb.dtb\0" \
  564. "bdev=sda3\0"
  565. /*
  566. * For emulation this causes u-boot to jump to the start of the
  567. * proof point app code automatically
  568. */
  569. #define CONFIG_PROOF_POINTS \
  570. "setenv bootargs root=/dev/$bdev rw " \
  571. "console=$consoledev,$baudrate $othbootargs;" \
  572. "cpu 1 release 0x29000000 - - -;" \
  573. "cpu 2 release 0x29000000 - - -;" \
  574. "cpu 3 release 0x29000000 - - -;" \
  575. "cpu 4 release 0x29000000 - - -;" \
  576. "cpu 5 release 0x29000000 - - -;" \
  577. "cpu 6 release 0x29000000 - - -;" \
  578. "cpu 7 release 0x29000000 - - -;" \
  579. "go 0x29000000"
  580. #define CONFIG_HVBOOT \
  581. "setenv bootargs config-addr=0x60000000; " \
  582. "bootm 0x01000000 - 0x00f00000"
  583. #define CONFIG_ALU \
  584. "setenv bootargs root=/dev/$bdev rw " \
  585. "console=$consoledev,$baudrate $othbootargs;" \
  586. "cpu 1 release 0x01000000 - - -;" \
  587. "cpu 2 release 0x01000000 - - -;" \
  588. "cpu 3 release 0x01000000 - - -;" \
  589. "cpu 4 release 0x01000000 - - -;" \
  590. "cpu 5 release 0x01000000 - - -;" \
  591. "cpu 6 release 0x01000000 - - -;" \
  592. "cpu 7 release 0x01000000 - - -;" \
  593. "go 0x01000000"
  594. #define CONFIG_LINUX \
  595. "setenv bootargs root=/dev/ram rw " \
  596. "console=$consoledev,$baudrate $othbootargs;" \
  597. "setenv ramdiskaddr 0x02000000;" \
  598. "setenv fdtaddr 0x00c00000;" \
  599. "setenv loadaddr 0x1000000;" \
  600. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  601. #define CONFIG_HDBOOT \
  602. "setenv bootargs root=/dev/$bdev rw " \
  603. "console=$consoledev,$baudrate $othbootargs;" \
  604. "tftp $loadaddr $bootfile;" \
  605. "tftp $fdtaddr $fdtfile;" \
  606. "bootm $loadaddr - $fdtaddr"
  607. #define CONFIG_NFSBOOTCOMMAND \
  608. "setenv bootargs root=/dev/nfs rw " \
  609. "nfsroot=$serverip:$rootpath " \
  610. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  611. "console=$consoledev,$baudrate $othbootargs;" \
  612. "tftp $loadaddr $bootfile;" \
  613. "tftp $fdtaddr $fdtfile;" \
  614. "bootm $loadaddr - $fdtaddr"
  615. #define CONFIG_RAMBOOTCOMMAND \
  616. "setenv bootargs root=/dev/ram rw " \
  617. "console=$consoledev,$baudrate $othbootargs;" \
  618. "tftp $ramdiskaddr $ramdiskfile;" \
  619. "tftp $loadaddr $bootfile;" \
  620. "tftp $fdtaddr $fdtfile;" \
  621. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  622. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  623. #include <asm/fsl_secure_boot.h>
  624. #endif /* __T2080RDB_H */