T102xRDB.h 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * T1024/T1023 RDB board configuration file
  8. */
  9. #ifndef __T1024RDB_H
  10. #define __T1024RDB_H
  11. #include <linux/stringify.h>
  12. /* High Level Configuration Options */
  13. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  14. #define CONFIG_ENABLE_36BIT_PHYS
  15. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  16. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  17. /* support deep sleep */
  18. #ifdef CONFIG_ARCH_T1024
  19. #define CONFIG_DEEP_SLEEP
  20. #endif
  21. #ifdef CONFIG_RAMBOOT_PBL
  22. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  23. #define CONFIG_SPL_FLUSH_IMAGE
  24. #define CONFIG_SPL_PAD_TO 0x40000
  25. #define CONFIG_SPL_MAX_SIZE 0x28000
  26. #define RESET_VECTOR_OFFSET 0x27FFC
  27. #define BOOT_PAGE_OFFSET 0x27000
  28. #ifdef CONFIG_SPL_BUILD
  29. #define CONFIG_SPL_SKIP_RELOCATE
  30. #define CONFIG_SPL_COMMON_INIT_DDR
  31. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  32. #endif
  33. #ifdef CONFIG_MTD_RAW_NAND
  34. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  35. #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  36. #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
  37. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  38. #if defined(CONFIG_TARGET_T1024RDB)
  39. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  40. #elif defined(CONFIG_TARGET_T1023RDB)
  41. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  42. #endif
  43. #endif
  44. #ifdef CONFIG_SPIFLASH
  45. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  46. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  47. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  48. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  49. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
  50. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  51. #ifndef CONFIG_SPL_BUILD
  52. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  53. #endif
  54. #if defined(CONFIG_TARGET_T1024RDB)
  55. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  56. #elif defined(CONFIG_TARGET_T1023RDB)
  57. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  58. #endif
  59. #endif
  60. #ifdef CONFIG_SDCARD
  61. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  62. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  63. #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  64. #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
  65. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  66. #ifndef CONFIG_SPL_BUILD
  67. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  68. #endif
  69. #if defined(CONFIG_TARGET_T1024RDB)
  70. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  71. #elif defined(CONFIG_TARGET_T1023RDB)
  72. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  73. #endif
  74. #endif
  75. #endif /* CONFIG_RAMBOOT_PBL */
  76. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  77. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  78. #endif
  79. /* PCIe Boot - Master */
  80. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  81. /*
  82. * for slave u-boot IMAGE instored in master memory space,
  83. * PHYS must be aligned based on the SIZE
  84. */
  85. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  86. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  87. #ifdef CONFIG_PHYS_64BIT
  88. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  89. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  90. #else
  91. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  92. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  93. #endif
  94. /*
  95. * for slave UCODE and ENV instored in master memory space,
  96. * PHYS must be aligned based on the SIZE
  97. */
  98. #ifdef CONFIG_PHYS_64BIT
  99. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  100. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  101. #else
  102. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  103. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
  104. #endif
  105. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  106. /* slave core release by master*/
  107. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  108. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  109. /* PCIe Boot - Slave */
  110. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  111. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  112. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  113. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  114. /* Set 1M boot space for PCIe boot */
  115. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  116. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  117. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  118. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  119. #endif
  120. #ifndef __ASSEMBLY__
  121. unsigned long get_board_sys_clk(void);
  122. unsigned long get_board_ddr_clk(void);
  123. #endif
  124. #define CONFIG_SYS_CLK_FREQ 100000000
  125. #define CONFIG_DDR_CLK_FREQ 100000000
  126. /*
  127. * These can be toggled for performance analysis, otherwise use default.
  128. */
  129. #define CONFIG_SYS_CACHE_STASHING
  130. #define CONFIG_BACKSIDE_L2_CACHE
  131. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  132. #define CONFIG_BTB /* toggle branch predition */
  133. #define CONFIG_DDR_ECC
  134. #ifdef CONFIG_DDR_ECC
  135. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  136. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  137. #endif
  138. /*
  139. * Config the L3 Cache as L3 SRAM
  140. */
  141. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  142. #define CONFIG_SYS_L3_SIZE (256 << 10)
  143. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  144. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  145. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  146. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  147. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  148. #ifdef CONFIG_PHYS_64BIT
  149. #define CONFIG_SYS_DCSRBAR 0xf0000000
  150. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  151. #endif
  152. /* EEPROM */
  153. #define CONFIG_ID_EEPROM
  154. #define CONFIG_SYS_I2C_EEPROM_NXID
  155. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  156. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  157. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  158. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  159. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  160. /*
  161. * DDR Setup
  162. */
  163. #define CONFIG_VERY_BIG_RAM
  164. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  165. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  166. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  167. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  168. #if defined(CONFIG_TARGET_T1024RDB)
  169. #define CONFIG_DDR_SPD
  170. #define CONFIG_SYS_SPD_BUS_NUM 0
  171. #define SPD_EEPROM_ADDRESS 0x51
  172. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  173. #elif defined(CONFIG_TARGET_T1023RDB)
  174. #define CONFIG_SYS_DDR_RAW_TIMING
  175. #define CONFIG_SYS_SDRAM_SIZE 2048
  176. #endif
  177. /*
  178. * IFC Definitions
  179. */
  180. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  181. #ifdef CONFIG_PHYS_64BIT
  182. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  183. #else
  184. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  185. #endif
  186. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  187. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  188. CSPR_PORT_SIZE_16 | \
  189. CSPR_MSEL_NOR | \
  190. CSPR_V)
  191. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  192. /* NOR Flash Timing Params */
  193. #if defined(CONFIG_TARGET_T1024RDB)
  194. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  195. #elif defined(CONFIG_TARGET_T1023RDB)
  196. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
  197. CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
  198. #endif
  199. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  200. FTIM0_NOR_TEADC(0x5) | \
  201. FTIM0_NOR_TEAHC(0x5))
  202. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  203. FTIM1_NOR_TRAD_NOR(0x1A) |\
  204. FTIM1_NOR_TSEQRAD_NOR(0x13))
  205. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  206. FTIM2_NOR_TCH(0x4) | \
  207. FTIM2_NOR_TWPH(0x0E) | \
  208. FTIM2_NOR_TWP(0x1c))
  209. #define CONFIG_SYS_NOR_FTIM3 0x0
  210. #define CONFIG_SYS_FLASH_QUIET_TEST
  211. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  212. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  213. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  214. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  215. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  216. #define CONFIG_SYS_FLASH_EMPTY_INFO
  217. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  218. #ifdef CONFIG_TARGET_T1024RDB
  219. /* CPLD on IFC */
  220. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  221. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  222. #define CONFIG_SYS_CSPR2_EXT (0xf)
  223. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  224. | CSPR_PORT_SIZE_8 \
  225. | CSPR_MSEL_GPCM \
  226. | CSPR_V)
  227. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  228. #define CONFIG_SYS_CSOR2 0x0
  229. /* CPLD Timing parameters for IFC CS2 */
  230. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  231. FTIM0_GPCM_TEADC(0x0e) | \
  232. FTIM0_GPCM_TEAHC(0x0e))
  233. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  234. FTIM1_GPCM_TRAD(0x1f))
  235. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  236. FTIM2_GPCM_TCH(0x8) | \
  237. FTIM2_GPCM_TWP(0x1f))
  238. #define CONFIG_SYS_CS2_FTIM3 0x0
  239. #endif
  240. /* NAND Flash on IFC */
  241. #define CONFIG_NAND_FSL_IFC
  242. #define CONFIG_SYS_NAND_BASE 0xff800000
  243. #ifdef CONFIG_PHYS_64BIT
  244. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  245. #else
  246. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  247. #endif
  248. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  249. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  250. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  251. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  252. | CSPR_V)
  253. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  254. #if defined(CONFIG_TARGET_T1024RDB)
  255. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  256. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  257. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  258. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  259. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  260. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  261. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  262. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  263. #elif defined(CONFIG_TARGET_T1023RDB)
  264. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  265. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  266. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  267. | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
  268. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  269. | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
  270. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  271. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  272. #endif
  273. #define CONFIG_SYS_NAND_ONFI_DETECTION
  274. /* ONFI NAND Flash mode0 Timing Params */
  275. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  276. FTIM0_NAND_TWP(0x18) | \
  277. FTIM0_NAND_TWCHT(0x07) | \
  278. FTIM0_NAND_TWH(0x0a))
  279. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  280. FTIM1_NAND_TWBE(0x39) | \
  281. FTIM1_NAND_TRR(0x0e) | \
  282. FTIM1_NAND_TRP(0x18))
  283. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  284. FTIM2_NAND_TREH(0x0a) | \
  285. FTIM2_NAND_TWHRE(0x1e))
  286. #define CONFIG_SYS_NAND_FTIM3 0x0
  287. #define CONFIG_SYS_NAND_DDR_LAW 11
  288. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  289. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  290. #if defined(CONFIG_MTD_RAW_NAND)
  291. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  292. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  293. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  294. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  295. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  296. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  297. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  298. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  299. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  300. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  301. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  302. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  303. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  304. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  305. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  306. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  307. #else
  308. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  309. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  310. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  311. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  312. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  313. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  314. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  315. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  316. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  317. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  318. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  319. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  320. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  321. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  322. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  323. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  324. #endif
  325. #ifdef CONFIG_SPL_BUILD
  326. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  327. #else
  328. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  329. #endif
  330. #if defined(CONFIG_RAMBOOT_PBL)
  331. #define CONFIG_SYS_RAMBOOT
  332. #endif
  333. #define CONFIG_HWCONFIG
  334. /* define to use L1 as initial stack */
  335. #define CONFIG_L1_INIT_RAM
  336. #define CONFIG_SYS_INIT_RAM_LOCK
  337. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  338. #ifdef CONFIG_PHYS_64BIT
  339. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  340. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  341. /* The assembler doesn't like typecast */
  342. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  343. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  344. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  345. #else
  346. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
  347. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  348. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  349. #endif
  350. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  351. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  352. GENERATED_GBL_DATA_SIZE)
  353. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  354. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  355. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  356. /* Serial Port */
  357. #define CONFIG_SYS_NS16550_SERIAL
  358. #define CONFIG_SYS_NS16550_REG_SIZE 1
  359. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  360. #define CONFIG_SYS_BAUDRATE_TABLE \
  361. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  362. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  363. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  364. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  365. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  366. /* Video */
  367. #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
  368. #ifdef CONFIG_FSL_DIU_FB
  369. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  370. #define CONFIG_VIDEO_LOGO
  371. #define CONFIG_VIDEO_BMP_LOGO
  372. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  373. /*
  374. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  375. * disable empty flash sector detection, which is I/O-intensive.
  376. */
  377. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  378. #endif
  379. /* I2C */
  380. #ifndef CONFIG_DM_I2C
  381. #define CONFIG_SYS_I2C
  382. #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  383. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  384. #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
  385. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  386. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  387. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  388. #else
  389. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  390. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  391. #endif
  392. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  393. #define I2C_PCA6408_BUS_NUM 1
  394. #define I2C_PCA6408_ADDR 0x20
  395. /* I2C bus multiplexer */
  396. #define I2C_MUX_CH_DEFAULT 0x8
  397. /*
  398. * RTC configuration
  399. */
  400. #define RTC
  401. #define CONFIG_RTC_DS1337 1
  402. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  403. /*
  404. * eSPI - Enhanced SPI
  405. */
  406. /*
  407. * General PCIe
  408. * Memory space is mapped 1-1, but I/O space must start from 0.
  409. */
  410. #define CONFIG_PCIE1 /* PCIE controller 1 */
  411. #define CONFIG_PCIE2 /* PCIE controller 2 */
  412. #define CONFIG_PCIE3 /* PCIE controller 3 */
  413. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  414. #ifdef CONFIG_PCI
  415. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  416. #ifdef CONFIG_PCIE1
  417. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  418. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  419. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  420. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  421. #endif
  422. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  423. #ifdef CONFIG_PCIE2
  424. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  425. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  426. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  427. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  428. #endif
  429. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  430. #ifdef CONFIG_PCIE3
  431. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  432. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  433. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  434. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  435. #endif
  436. #if !defined(CONFIG_DM_PCI)
  437. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  438. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  439. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  440. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  441. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  442. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  443. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  444. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  445. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  446. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  447. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  448. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  449. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  450. #define CONFIG_PCI_INDIRECT_BRIDGE
  451. #endif
  452. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  453. #endif /* CONFIG_PCI */
  454. /*
  455. * USB
  456. */
  457. #define CONFIG_HAS_FSL_DR_USB
  458. #ifdef CONFIG_HAS_FSL_DR_USB
  459. #define CONFIG_USB_EHCI_FSL
  460. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  461. #endif
  462. /*
  463. * SDHC
  464. */
  465. #ifdef CONFIG_MMC
  466. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  467. #endif
  468. /* Qman/Bman */
  469. #ifndef CONFIG_NOBQFMAN
  470. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  471. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  472. #ifdef CONFIG_PHYS_64BIT
  473. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  474. #else
  475. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  476. #endif
  477. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  478. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  479. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  480. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  481. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  482. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  483. CONFIG_SYS_BMAN_CENA_SIZE)
  484. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  485. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  486. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  487. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  488. #ifdef CONFIG_PHYS_64BIT
  489. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  490. #else
  491. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  492. #endif
  493. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  494. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  495. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  496. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  497. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  498. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  499. CONFIG_SYS_QMAN_CENA_SIZE)
  500. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  501. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  502. #define CONFIG_SYS_DPAA_FMAN
  503. /* Default address of microcode for the Linux FMan driver */
  504. #if defined(CONFIG_SPIFLASH)
  505. /*
  506. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  507. * env, so we got 0x110000.
  508. */
  509. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  510. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  511. #elif defined(CONFIG_SDCARD)
  512. /*
  513. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  514. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  515. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  516. */
  517. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  518. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  519. #elif defined(CONFIG_MTD_RAW_NAND)
  520. #if defined(CONFIG_TARGET_T1024RDB)
  521. #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  522. #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  523. #elif defined(CONFIG_TARGET_T1023RDB)
  524. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  525. #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
  526. #endif
  527. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  528. /*
  529. * Slave has no ucode locally, it can fetch this from remote. When implementing
  530. * in two corenet boards, slave's ucode could be stored in master's memory
  531. * space, the address can be mapped from slave TLB->slave LAW->
  532. * slave SRIO or PCIE outbound window->master inbound window->
  533. * master LAW->the ucode address in master's memory space.
  534. */
  535. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  536. #else
  537. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  538. #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
  539. #endif
  540. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  541. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  542. #endif /* CONFIG_NOBQFMAN */
  543. #ifdef CONFIG_SYS_DPAA_FMAN
  544. #if defined(CONFIG_TARGET_T1024RDB)
  545. #define RGMII_PHY1_ADDR 0x2
  546. #define RGMII_PHY2_ADDR 0x6
  547. #define SGMII_AQR_PHY_ADDR 0x2
  548. #define FM1_10GEC1_PHY_ADDR 0x1
  549. #elif defined(CONFIG_TARGET_T1023RDB)
  550. #define RGMII_PHY1_ADDR 0x1
  551. #define SGMII_RTK_PHY_ADDR 0x3
  552. #define SGMII_AQR_PHY_ADDR 0x2
  553. #endif
  554. #endif
  555. #ifdef CONFIG_FMAN_ENET
  556. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  557. #endif
  558. /*
  559. * Dynamic MTD Partition support with mtdparts
  560. */
  561. /*
  562. * Environment
  563. */
  564. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  565. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  566. /*
  567. * Miscellaneous configurable options
  568. */
  569. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  570. /*
  571. * For booting Linux, the board info and command line data
  572. * have to be in the first 64 MB of memory, since this is
  573. * the maximum mapped by the Linux kernel during initialization.
  574. */
  575. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  576. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  577. #ifdef CONFIG_CMD_KGDB
  578. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  579. #endif
  580. /*
  581. * Environment Configuration
  582. */
  583. #define CONFIG_ROOTPATH "/opt/nfsroot"
  584. #define CONFIG_BOOTFILE "uImage"
  585. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  586. #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
  587. #define __USB_PHY_TYPE utmi
  588. #ifdef CONFIG_ARCH_T1024
  589. #define CONFIG_BOARDNAME t1024rdb
  590. #define BANK_INTLV cs0_cs1
  591. #else
  592. #define CONFIG_BOARDNAME t1023rdb
  593. #define BANK_INTLV null
  594. #endif
  595. #define CONFIG_EXTRA_ENV_SETTINGS \
  596. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  597. "bank_intlv=" __stringify(BANK_INTLV) "\0" \
  598. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  599. "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
  600. "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
  601. __stringify(CONFIG_BOARDNAME) ".dtb\0" \
  602. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  603. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  604. "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
  605. "netdev=eth0\0" \
  606. "tftpflash=tftpboot $loadaddr $uboot && " \
  607. "protect off $ubootaddr +$filesize && " \
  608. "erase $ubootaddr +$filesize && " \
  609. "cp.b $loadaddr $ubootaddr $filesize && " \
  610. "protect on $ubootaddr +$filesize && " \
  611. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  612. "consoledev=ttyS0\0" \
  613. "ramdiskaddr=2000000\0" \
  614. "fdtaddr=1e00000\0" \
  615. "bdev=sda3\0"
  616. #define CONFIG_LINUX \
  617. "setenv bootargs root=/dev/ram rw " \
  618. "console=$consoledev,$baudrate $othbootargs;" \
  619. "setenv ramdiskaddr 0x02000000;" \
  620. "setenv fdtaddr 0x00c00000;" \
  621. "setenv loadaddr 0x1000000;" \
  622. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  623. #define CONFIG_NFSBOOTCOMMAND \
  624. "setenv bootargs root=/dev/nfs rw " \
  625. "nfsroot=$serverip:$rootpath " \
  626. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  627. "console=$consoledev,$baudrate $othbootargs;" \
  628. "tftp $loadaddr $bootfile;" \
  629. "tftp $fdtaddr $fdtfile;" \
  630. "bootm $loadaddr - $fdtaddr"
  631. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  632. #include <asm/fsl_secure_boot.h>
  633. #endif /* __T1024RDB_H */