MPC8610HPCD.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * MPC8610HPCD board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <linux/stringify.h>
  11. /* High Level Configuration Options */
  12. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  13. /* video */
  14. #define CONFIG_FSL_DIU_FB
  15. #ifdef CONFIG_FSL_DIU_FB
  16. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
  17. #define CONFIG_VIDEO_LOGO
  18. #define CONFIG_VIDEO_BMP_LOGO
  19. #endif
  20. #ifdef RUN_DIAG
  21. #define CONFIG_SYS_DIAG_ADDR 0xff800000
  22. #endif
  23. /*
  24. * virtual address to be used for temporary mappings. There
  25. * should be 128k free at this VA.
  26. */
  27. #define CONFIG_SYS_SCRATCH_VA 0xc0000000
  28. #define CONFIG_PCI1 1 /* PCI controller 1 */
  29. #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
  30. #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
  31. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  32. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  33. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  34. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  35. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  36. #define CONFIG_ALTIVEC 1
  37. /*
  38. * L2CR setup -- make sure this is right for your board!
  39. */
  40. #define CONFIG_SYS_L2
  41. #define L2_INIT 0
  42. #define L2_ENABLE (L2CR_L2E |0x00100000 )
  43. #ifndef CONFIG_SYS_CLK_FREQ
  44. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  45. #endif
  46. /*
  47. * Base addresses -- Note these are effective addresses where the
  48. * actual resources get mapped (not physical addresses)
  49. */
  50. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  51. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  52. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  53. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  54. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
  55. /* DDR Setup */
  56. #define CONFIG_SPD_EEPROM /* Use SPD for DDR */
  57. #define CONFIG_DDR_SPD
  58. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  59. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  60. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  61. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  62. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  63. #define CONFIG_VERY_BIG_RAM
  64. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  65. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  66. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  67. /* These are used when DDR doesn't use SPD. */
  68. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  69. #if 0 /* TODO */
  70. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  71. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
  72. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  73. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  74. #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  75. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  76. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  77. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  78. #define CONFIG_SYS_DDR_INTERVAL 0x06180100
  79. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  80. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  81. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  82. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  83. #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
  84. #define CONFIG_SYS_DDR_CONTROL2 0x04400010
  85. #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
  86. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  87. #define CONFIG_SYS_DDR_SBE 0x000f0000
  88. #endif
  89. #define CONFIG_ID_EEPROM
  90. #define CONFIG_SYS_I2C_EEPROM_NXID
  91. #define CONFIG_ID_EEPROM
  92. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  93. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  94. #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
  95. #define CONFIG_SYS_FLASH_BASE2 0xf8000000
  96. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  97. #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
  98. #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
  99. #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
  100. #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
  101. #if 0 /* TODO */
  102. #define CONFIG_SYS_BR2_PRELIM 0xf0000000
  103. #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
  104. #endif
  105. #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
  106. #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
  107. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  108. #define PIXIS_BASE 0xe8000000 /* PIXIS registers */
  109. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  110. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  111. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  112. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  113. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
  114. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  115. #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
  116. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  117. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  118. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  119. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  120. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  121. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  122. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  123. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  124. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
  125. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  126. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  127. #undef CONFIG_SYS_FLASH_CHECKSUM
  128. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  129. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  130. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  131. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  132. #define CONFIG_SYS_FLASH_EMPTY_INFO
  133. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  134. #define CONFIG_SYS_RAMBOOT
  135. #else
  136. #undef CONFIG_SYS_RAMBOOT
  137. #endif
  138. #if defined(CONFIG_SYS_RAMBOOT)
  139. #undef CONFIG_SPD_EEPROM
  140. #define CONFIG_SYS_SDRAM_SIZE 256
  141. #endif
  142. #define CONFIG_SYS_INIT_RAM_LOCK 1
  143. #ifndef CONFIG_SYS_INIT_RAM_LOCK
  144. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  145. #else
  146. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
  147. #endif
  148. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  149. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  150. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  151. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  152. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
  153. /* Serial Port */
  154. #define CONFIG_SYS_NS16550_SERIAL
  155. #define CONFIG_SYS_NS16550_REG_SIZE 1
  156. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  157. #define CONFIG_SYS_BAUDRATE_TABLE \
  158. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  159. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  160. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  161. /* maximum size of the flat tree (8K) */
  162. #define OF_FLAT_TREE_MAX_SIZE 8192
  163. /*
  164. * I2C
  165. */
  166. #define CONFIG_SYS_I2C
  167. #define CONFIG_SYS_I2C_FSL
  168. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  169. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  170. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  171. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  172. /*
  173. * General PCI
  174. * Addresses are mapped 1-1.
  175. */
  176. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  177. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  178. #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
  179. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  180. #define CONFIG_SYS_PCI1_IO_BUS 0x0000000
  181. #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
  182. #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
  183. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  184. /* controller 1, Base address 0xa000 */
  185. #define CONFIG_SYS_PCIE1_NAME "ULI"
  186. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  187. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  188. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  189. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  190. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
  191. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
  192. /* controller 2, Base Address 0x9000 */
  193. #define CONFIG_SYS_PCIE2_NAME "Slot 1"
  194. #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
  195. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
  196. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  197. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
  198. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
  199. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
  200. #if defined(CONFIG_PCI)
  201. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  202. #define CONFIG_ULI526X
  203. /************************************************************
  204. * USB support
  205. ************************************************************/
  206. #define CONFIG_PCI_OHCI 1
  207. #define CONFIG_USB_OHCI_NEW 1
  208. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  209. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  210. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  211. #if !defined(CONFIG_PCI_PNP)
  212. #define PCI_ENET0_IOADDR 0xe0000000
  213. #define PCI_ENET0_MEMADDR 0xe0000000
  214. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  215. #endif
  216. #ifdef CONFIG_SCSI_AHCI
  217. #define CONFIG_SATA_ULI5288
  218. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  219. #define CONFIG_SYS_SCSI_MAX_LUN 1
  220. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  221. #endif
  222. #endif /* CONFIG_PCI */
  223. /*
  224. * BAT0 2G Cacheable, non-guarded
  225. * 0x0000_0000 2G DDR
  226. */
  227. #define CONFIG_SYS_DBAT0L (BATL_PP_RW)
  228. #define CONFIG_SYS_IBAT0L (BATL_PP_RW)
  229. /*
  230. * BAT1 1G Cache-inhibited, guarded
  231. * 0x8000_0000 256M PCI-1 Memory
  232. * 0xa000_0000 256M PCI-Express 1 Memory
  233. * 0x9000_0000 256M PCI-Express 2 Memory
  234. */
  235. #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
  236. | BATL_GUARDEDSTORAGE)
  237. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
  238. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  239. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  240. /*
  241. * BAT2 16M Cache-inhibited, guarded
  242. * 0xe100_0000 1M PCI-1 I/O
  243. */
  244. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
  245. | BATL_GUARDEDSTORAGE)
  246. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
  247. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  248. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  249. /*
  250. * BAT3 4M Cache-inhibited, guarded
  251. * 0xe000_0000 4M CCSR
  252. */
  253. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
  254. | BATL_GUARDEDSTORAGE)
  255. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
  256. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
  257. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  258. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  259. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  260. | BATL_PP_RW | BATL_CACHEINHIBIT \
  261. | BATL_GUARDEDSTORAGE)
  262. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
  263. | BATU_BL_1M | BATU_VS | BATU_VP)
  264. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  265. | BATL_PP_RW | BATL_CACHEINHIBIT)
  266. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  267. #endif
  268. /*
  269. * BAT4 32M Cache-inhibited, guarded
  270. * 0xe200_0000 1M PCI-Express 2 I/O
  271. * 0xe300_0000 1M PCI-Express 1 I/O
  272. */
  273. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
  274. | BATL_GUARDEDSTORAGE)
  275. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
  276. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  277. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  278. /*
  279. * BAT5 128K Cacheable, non-guarded
  280. * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
  281. */
  282. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  283. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  284. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  285. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  286. /*
  287. * BAT6 256M Cache-inhibited, guarded
  288. * 0xf000_0000 256M FLASH
  289. */
  290. #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
  291. | BATL_GUARDEDSTORAGE)
  292. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  293. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
  294. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  295. /* Map the last 1M of flash where we're running from reset */
  296. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  297. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  298. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  299. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  300. | BATL_MEMCOHERENCE)
  301. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  302. /*
  303. * BAT7 4M Cache-inhibited, guarded
  304. * 0xe800_0000 4M PIXIS
  305. */
  306. #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
  307. | BATL_GUARDEDSTORAGE)
  308. #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  309. #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  310. #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
  311. /*
  312. * Environment
  313. */
  314. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  315. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  316. /*
  317. * BOOTP options
  318. */
  319. #define CONFIG_BOOTP_BOOTFILESIZE
  320. #define CONFIG_WATCHDOG /* watchdog enabled */
  321. #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
  322. /*
  323. * Miscellaneous configurable options
  324. */
  325. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  326. /*
  327. * For booting Linux, the board info and command line data
  328. * have to be in the first 8 MB of memory, since this is
  329. * the maximum mapped by the Linux kernel during initialization.
  330. */
  331. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
  332. #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
  333. #if defined(CONFIG_CMD_KGDB)
  334. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  335. #endif
  336. /*
  337. * Environment Configuration
  338. */
  339. #define CONFIG_IPADDR 192.168.1.100
  340. #define CONFIG_HOSTNAME "unknown"
  341. #define CONFIG_ROOTPATH "/opt/nfsroot"
  342. #define CONFIG_BOOTFILE "uImage"
  343. #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
  344. #define CONFIG_SERVERIP 192.168.1.1
  345. #define CONFIG_GATEWAYIP 192.168.1.1
  346. #define CONFIG_NETMASK 255.255.255.0
  347. /* default location for tftp and bootm */
  348. #define CONFIG_LOADADDR 0x10000000
  349. #if defined(CONFIG_PCI1)
  350. #define PCI_ENV \
  351. "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
  352. "echo e;md ${a}e00 9\0" \
  353. "pci1regs=setenv a e0008; run pcireg\0" \
  354. "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
  355. "pci d.w $b.0 56 1\0" \
  356. "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
  357. "pci w.w $b.0 56 ffff\0" \
  358. "pci1err=setenv a e0008; run pcierr\0" \
  359. "pci1errc=setenv a e0008; run pcierrc\0"
  360. #else
  361. #define PCI_ENV ""
  362. #endif
  363. #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
  364. #define PCIE_ENV \
  365. "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
  366. "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
  367. "pcie1regs=setenv a e000a; run pciereg\0" \
  368. "pcie2regs=setenv a e0009; run pciereg\0" \
  369. "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
  370. "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
  371. "pci d $b.0 130 1\0" \
  372. "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
  373. "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
  374. "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
  375. "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
  376. "pcie1err=setenv a e000a; run pcieerr\0" \
  377. "pcie2err=setenv a e0009; run pcieerr\0" \
  378. "pcie1errc=setenv a e000a; run pcieerrc\0" \
  379. "pcie2errc=setenv a e0009; run pcieerrc\0"
  380. #else
  381. #define PCIE_ENV ""
  382. #endif
  383. #define DMA_ENV \
  384. "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
  385. "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
  386. "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
  387. "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
  388. "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
  389. "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
  390. "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
  391. "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
  392. #ifdef ENV_DEBUG
  393. #define CONFIG_EXTRA_ENV_SETTINGS \
  394. "netdev=eth0\0" \
  395. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  396. "tftpflash=tftpboot $loadaddr $uboot; " \
  397. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  398. " +$filesize; " \
  399. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  400. " +$filesize; " \
  401. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  402. " $filesize; " \
  403. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  404. " +$filesize; " \
  405. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  406. " $filesize\0" \
  407. "consoledev=ttyS0\0" \
  408. "ramdiskaddr=0x18000000\0" \
  409. "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
  410. "fdtaddr=0x17c00000\0" \
  411. "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
  412. "bdev=sda3\0" \
  413. "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
  414. "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
  415. "maxcpus=1" \
  416. "eoi=mw e00400b0 0\0" \
  417. "iack=md e00400a0 1\0" \
  418. "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
  419. "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
  420. "md ${a}f00 5\0" \
  421. "ddr1regs=setenv a e0002; run ddrreg\0" \
  422. "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
  423. "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
  424. "md ${a}e60 1; md ${a}ef0 1d\0" \
  425. "guregs=setenv a e00e0; run gureg\0" \
  426. "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
  427. "mcmregs=setenv a e0001; run mcmreg\0" \
  428. "diuregs=md e002c000 1d\0" \
  429. "dium=mw e002c01c\0" \
  430. "diuerr=md e002c014 1\0" \
  431. "pmregs=md e00e1000 2b\0" \
  432. "lawregs=md e0000c08 4b\0" \
  433. "lbcregs=md e0005000 36\0" \
  434. "dma0regs=md e0021100 12\0" \
  435. "dma1regs=md e0021180 12\0" \
  436. "dma2regs=md e0021200 12\0" \
  437. "dma3regs=md e0021280 12\0" \
  438. PCI_ENV \
  439. PCIE_ENV \
  440. DMA_ENV
  441. #else
  442. #define CONFIG_EXTRA_ENV_SETTINGS \
  443. "netdev=eth0\0" \
  444. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  445. "consoledev=ttyS0\0" \
  446. "ramdiskaddr=0x18000000\0" \
  447. "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
  448. "fdtaddr=0x17c00000\0" \
  449. "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
  450. "bdev=sda3\0"
  451. #endif
  452. #define CONFIG_NFSBOOTCOMMAND \
  453. "setenv bootargs root=/dev/nfs rw " \
  454. "nfsroot=$serverip:$rootpath " \
  455. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  456. "console=$consoledev,$baudrate $othbootargs;" \
  457. "tftp $loadaddr $bootfile;" \
  458. "tftp $fdtaddr $fdtfile;" \
  459. "bootm $loadaddr - $fdtaddr"
  460. #define CONFIG_RAMBOOTCOMMAND \
  461. "setenv bootargs root=/dev/ram rw " \
  462. "console=$consoledev,$baudrate $othbootargs;" \
  463. "tftp $ramdiskaddr $ramdiskfile;" \
  464. "tftp $loadaddr $bootfile;" \
  465. "tftp $fdtaddr $fdtfile;" \
  466. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  467. #define CONFIG_BOOTCOMMAND \
  468. "setenv bootargs root=/dev/$bdev rw " \
  469. "console=$consoledev,$baudrate $othbootargs;" \
  470. "tftp $loadaddr $bootfile;" \
  471. "tftp $fdtaddr $fdtfile;" \
  472. "bootm $loadaddr - $fdtaddr"
  473. #endif /* __CONFIG_H */