MPC8555CDS.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. */
  5. /*
  6. * mpc8555cds board configuration file
  7. *
  8. * Please refer to doc/README.mpc85xxcds for more info.
  9. *
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /* High Level Configuration Options */
  14. #define CONFIG_CPM2 1 /* has CPM2 */
  15. #define CONFIG_PCI_INDIRECT_BRIDGE
  16. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  17. #define CONFIG_FSL_VIA
  18. #ifndef __ASSEMBLY__
  19. extern unsigned long get_clock_freq(void);
  20. #endif
  21. #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  22. /*
  23. * These can be toggled for performance analysis, otherwise use default.
  24. */
  25. #define CONFIG_L2_CACHE /* toggle L2 cache */
  26. #define CONFIG_BTB /* toggle branch predition */
  27. #define CONFIG_SYS_CCSRBAR 0xe0000000
  28. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  29. /* DDR Setup */
  30. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  31. #define CONFIG_DDR_SPD
  32. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  33. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  34. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  35. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  36. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  37. /* I2C addresses of SPD EEPROMs */
  38. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  39. /* Make sure required options are set */
  40. #ifndef CONFIG_SPD_EEPROM
  41. #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  42. #endif
  43. /*
  44. * Local Bus Definitions
  45. */
  46. /*
  47. * FLASH on the Local Bus
  48. * Two banks, 8M each, using the CFI driver.
  49. * Boot from BR0/OR0 bank at 0xff00_0000
  50. * Alternate BR1/OR1 bank at 0xff80_0000
  51. *
  52. * BR0, BR1:
  53. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  54. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  55. * Port Size = 16 bits = BRx[19:20] = 10
  56. * Use GPCM = BRx[24:26] = 000
  57. * Valid = BRx[31] = 1
  58. *
  59. * 0 4 8 12 16 20 24 28
  60. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  61. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  62. *
  63. * OR0, OR1:
  64. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  65. * Reserved ORx[17:18] = 11, confusion here?
  66. * CSNT = ORx[20] = 1
  67. * ACS = half cycle delay = ORx[21:22] = 11
  68. * SCY = 6 = ORx[24:27] = 0110
  69. * TRLX = use relaxed timing = ORx[29] = 1
  70. * EAD = use external address latch delay = OR[31] = 1
  71. *
  72. * 0 4 8 12 16 20 24 28
  73. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  74. */
  75. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
  76. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  77. #define CONFIG_SYS_BR1_PRELIM 0xff001001
  78. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  79. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  80. #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
  81. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  82. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  83. #undef CONFIG_SYS_FLASH_CHECKSUM
  84. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  85. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  86. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  87. #define CONFIG_SYS_FLASH_EMPTY_INFO
  88. /*
  89. * SDRAM on the Local Bus
  90. */
  91. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  92. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  93. /*
  94. * Base Register 2 and Option Register 2 configure SDRAM.
  95. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  96. *
  97. * For BR2, need:
  98. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  99. * port-size = 32-bits = BR2[19:20] = 11
  100. * no parity checking = BR2[21:22] = 00
  101. * SDRAM for MSEL = BR2[24:26] = 011
  102. * Valid = BR[31] = 1
  103. *
  104. * 0 4 8 12 16 20 24 28
  105. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  106. *
  107. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  108. * FIXME: the top 17 bits of BR2.
  109. */
  110. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  111. /*
  112. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  113. *
  114. * For OR2, need:
  115. * 64MB mask for AM, OR2[0:7] = 1111 1100
  116. * XAM, OR2[17:18] = 11
  117. * 9 columns OR2[19-21] = 010
  118. * 13 rows OR2[23-25] = 100
  119. * EAD set for extra time OR[31] = 1
  120. *
  121. * 0 4 8 12 16 20 24 28
  122. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  123. */
  124. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  125. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  126. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  127. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  128. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  129. /*
  130. * Common settings for all Local Bus SDRAM commands.
  131. * At run time, either BSMA1516 (for CPU 1.1)
  132. * or BSMA1617 (for CPU 1.0) (old)
  133. * is OR'ed in too.
  134. */
  135. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  136. | LSDMR_PRETOACT7 \
  137. | LSDMR_ACTTORW7 \
  138. | LSDMR_BL8 \
  139. | LSDMR_WRC4 \
  140. | LSDMR_CL3 \
  141. | LSDMR_RFEN \
  142. )
  143. /*
  144. * The CADMUS registers are connected to CS3 on CDS.
  145. * The new memory map places CADMUS at 0xf8000000.
  146. *
  147. * For BR3, need:
  148. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  149. * port-size = 8-bits = BR[19:20] = 01
  150. * no parity checking = BR[21:22] = 00
  151. * GPMC for MSEL = BR[24:26] = 000
  152. * Valid = BR[31] = 1
  153. *
  154. * 0 4 8 12 16 20 24 28
  155. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  156. *
  157. * For OR3, need:
  158. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  159. * disable buffer ctrl OR[19] = 0
  160. * CSNT OR[20] = 1
  161. * ACS OR[21:22] = 11
  162. * XACS OR[23] = 1
  163. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  164. * SETA OR[28] = 0
  165. * TRLX OR[29] = 1
  166. * EHTR OR[30] = 1
  167. * EAD extra time OR[31] = 1
  168. *
  169. * 0 4 8 12 16 20 24 28
  170. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  171. */
  172. #define CONFIG_FSL_CADMUS
  173. #define CADMUS_BASE_ADDR 0xf8000000
  174. #define CONFIG_SYS_BR3_PRELIM 0xf8000801
  175. #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
  176. #define CONFIG_SYS_INIT_RAM_LOCK 1
  177. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  178. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  179. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  180. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  181. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  182. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  183. /* Serial Port */
  184. #define CONFIG_SYS_NS16550_SERIAL
  185. #define CONFIG_SYS_NS16550_REG_SIZE 1
  186. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  187. #define CONFIG_SYS_BAUDRATE_TABLE \
  188. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  189. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  190. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  191. /*
  192. * I2C
  193. */
  194. #define CONFIG_SYS_I2C
  195. #define CONFIG_SYS_I2C_FSL
  196. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  197. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  198. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  199. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  200. /* EEPROM */
  201. #define CONFIG_ID_EEPROM
  202. #define CONFIG_SYS_I2C_EEPROM_CCID
  203. #define CONFIG_SYS_ID_EEPROM
  204. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  205. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  206. /*
  207. * General PCI
  208. * Addresses are mapped 1-1.
  209. */
  210. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  211. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  212. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  213. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  214. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  215. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  216. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  217. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  218. #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  219. #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  220. #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
  221. #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
  222. #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
  223. #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
  224. #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
  225. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  226. #ifdef CONFIG_LEGACY
  227. #define BRIDGE_ID 17
  228. #define VIA_ID 2
  229. #else
  230. #define BRIDGE_ID 28
  231. #define VIA_ID 4
  232. #endif
  233. #if defined(CONFIG_PCI)
  234. #define CONFIG_MPC85XX_PCI2
  235. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  236. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  237. #endif /* CONFIG_PCI */
  238. #if defined(CONFIG_TSEC_ENET)
  239. #define CONFIG_TSEC1 1
  240. #define CONFIG_TSEC1_NAME "TSEC0"
  241. #define CONFIG_TSEC2 1
  242. #define CONFIG_TSEC2_NAME "TSEC1"
  243. #define TSEC1_PHY_ADDR 0
  244. #define TSEC2_PHY_ADDR 1
  245. #define TSEC1_PHYIDX 0
  246. #define TSEC2_PHYIDX 0
  247. #define TSEC1_FLAGS TSEC_GIGABIT
  248. #define TSEC2_FLAGS TSEC_GIGABIT
  249. /* Options are: TSEC[0-1] */
  250. #define CONFIG_ETHPRIME "TSEC0"
  251. #endif /* CONFIG_TSEC_ENET */
  252. /*
  253. * Environment
  254. */
  255. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  256. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  257. /*
  258. * BOOTP options
  259. */
  260. #define CONFIG_BOOTP_BOOTFILESIZE
  261. #undef CONFIG_WATCHDOG /* watchdog disabled */
  262. /*
  263. * Miscellaneous configurable options
  264. */
  265. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  266. /*
  267. * For booting Linux, the board info and command line data
  268. * have to be in the first 64 MB of memory, since this is
  269. * the maximum mapped by the Linux kernel during initialization.
  270. */
  271. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  272. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  273. #if defined(CONFIG_CMD_KGDB)
  274. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  275. #endif
  276. /*
  277. * Environment Configuration
  278. */
  279. #if defined(CONFIG_TSEC_ENET)
  280. #define CONFIG_HAS_ETH0
  281. #define CONFIG_HAS_ETH1
  282. #define CONFIG_HAS_ETH2
  283. #endif
  284. #define CONFIG_IPADDR 192.168.1.253
  285. #define CONFIG_HOSTNAME "unknown"
  286. #define CONFIG_ROOTPATH "/nfsroot"
  287. #define CONFIG_BOOTFILE "your.uImage"
  288. #define CONFIG_SERVERIP 192.168.1.1
  289. #define CONFIG_GATEWAYIP 192.168.1.1
  290. #define CONFIG_NETMASK 255.255.255.0
  291. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  292. #define CONFIG_EXTRA_ENV_SETTINGS \
  293. "netdev=eth0\0" \
  294. "consoledev=ttyS1\0" \
  295. "ramdiskaddr=600000\0" \
  296. "ramdiskfile=your.ramdisk.u-boot\0" \
  297. "fdtaddr=400000\0" \
  298. "fdtfile=your.fdt.dtb\0"
  299. #define CONFIG_NFSBOOTCOMMAND \
  300. "setenv bootargs root=/dev/nfs rw " \
  301. "nfsroot=$serverip:$rootpath " \
  302. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  303. "console=$consoledev,$baudrate $othbootargs;" \
  304. "tftp $loadaddr $bootfile;" \
  305. "tftp $fdtaddr $fdtfile;" \
  306. "bootm $loadaddr - $fdtaddr"
  307. #define CONFIG_RAMBOOTCOMMAND \
  308. "setenv bootargs root=/dev/ram rw " \
  309. "console=$consoledev,$baudrate $othbootargs;" \
  310. "tftp $ramdiskaddr $ramdiskfile;" \
  311. "tftp $loadaddr $bootfile;" \
  312. "bootm $loadaddr $ramdiskaddr"
  313. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  314. #endif /* __CONFIG_H */