MPC8544DS.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * mpc8544ds board configuration file
  7. *
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #define CONFIG_PCI1 1 /* PCI controller 1 */
  12. #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
  13. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
  14. #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
  15. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  16. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  17. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  18. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  19. #ifndef __ASSEMBLY__
  20. #include <linux/stringify.h>
  21. extern unsigned long get_board_sys_clk(unsigned long dummy);
  22. #endif
  23. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  24. /*
  25. * These can be toggled for performance analysis, otherwise use default.
  26. */
  27. #define CONFIG_L2_CACHE /* toggle L2 cache */
  28. #define CONFIG_BTB /* toggle branch predition */
  29. /*
  30. * Only possible on E500 Version 2 or newer cores.
  31. */
  32. #define CONFIG_ENABLE_36BIT_PHYS 1
  33. #define CONFIG_SYS_CCSRBAR 0xe0000000
  34. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  35. /* DDR Setup */
  36. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  37. #define CONFIG_DDR_SPD
  38. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  39. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  40. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  41. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  42. #define CONFIG_VERY_BIG_RAM
  43. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  44. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  45. /* I2C addresses of SPD EEPROMs */
  46. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  47. /* Make sure required options are set */
  48. #ifndef CONFIG_SPD_EEPROM
  49. #error ("CONFIG_SPD_EEPROM is required")
  50. #endif
  51. /*
  52. * Memory map
  53. *
  54. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  55. *
  56. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  57. *
  58. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  59. *
  60. * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
  61. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  62. *
  63. * Localbus cacheable
  64. *
  65. * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
  66. * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
  67. *
  68. * Localbus non-cacheable
  69. *
  70. * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
  71. * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
  72. * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
  73. *
  74. */
  75. /*
  76. * Local Bus Definitions
  77. */
  78. #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
  79. #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
  80. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  81. #define CONFIG_SYS_BR1_PRELIM 0xfe801001
  82. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  83. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  84. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  85. #define CONFIG_SYS_FLASH_QUIET_TEST
  86. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  87. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  88. #undef CONFIG_SYS_FLASH_CHECKSUM
  89. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  90. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  91. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  92. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  93. #define CONFIG_SYS_FLASH_EMPTY_INFO
  94. #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
  95. #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
  96. #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
  97. #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
  98. #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
  99. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  100. #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
  101. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  102. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  103. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  104. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  105. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
  106. * register */
  107. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  108. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  109. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  110. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  111. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  112. #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
  113. #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
  114. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  115. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  116. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  117. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  118. #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
  119. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
  120. #define PIXIS_VSPEED2_TSEC1SER 0x2
  121. #define PIXIS_VSPEED2_TSEC3SER 0x1
  122. #define PIXIS_VCFGEN1_TSEC1SER 0x20
  123. #define PIXIS_VCFGEN1_TSEC3SER 0x40
  124. #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
  125. #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
  126. #define CONFIG_SYS_INIT_RAM_LOCK 1
  127. #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
  128. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  129. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  130. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  131. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  132. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  133. /* Serial Port - controlled on board with jumper J8
  134. * open - index 2
  135. * shorted - index 1
  136. */
  137. #define CONFIG_SYS_NS16550_SERIAL
  138. #define CONFIG_SYS_NS16550_REG_SIZE 1
  139. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  140. #define CONFIG_SYS_BAUDRATE_TABLE \
  141. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  142. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  143. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  144. /* I2C */
  145. #define CONFIG_SYS_I2C
  146. #define CONFIG_SYS_I2C_FSL
  147. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  148. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  149. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  150. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  151. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  152. /*
  153. * General PCI
  154. * Memory space is mapped 1-1, but I/O space must start from 0.
  155. */
  156. #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
  157. #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
  158. #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
  159. #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
  160. #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
  161. #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
  162. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
  163. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  164. #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
  165. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  166. #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
  167. #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
  168. /* controller 2, Slot 1, tgtid 1, Base address 9000 */
  169. #define CONFIG_SYS_PCIE2_NAME "Slot 1"
  170. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
  171. #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
  172. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
  173. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  174. #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
  175. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  176. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
  177. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  178. /* controller 1, Slot 2,tgtid 2, Base address a000 */
  179. #define CONFIG_SYS_PCIE1_NAME "Slot 2"
  180. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  181. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  182. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  183. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  184. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
  185. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  186. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
  187. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  188. /* controller 3, direct to uli, tgtid 3, Base address b000 */
  189. #define CONFIG_SYS_PCIE3_NAME "ULI"
  190. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  191. #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
  192. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
  193. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
  194. #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
  195. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  196. #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
  197. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
  198. #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
  199. #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
  200. #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
  201. #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
  202. #if defined(CONFIG_PCI)
  203. /*PCIE video card used*/
  204. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
  205. /*PCI video card used*/
  206. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
  207. /* video */
  208. #if defined(CONFIG_VIDEO)
  209. #define CONFIG_BIOSEMU
  210. #define CONFIG_ATI_RADEON_FB
  211. #define CONFIG_VIDEO_LOGO
  212. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  213. #endif
  214. #ifndef CONFIG_PCI_PNP
  215. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  216. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
  217. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  218. #endif
  219. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  220. #ifdef CONFIG_SCSI_AHCI
  221. #define CONFIG_SATA_ULI5288
  222. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  223. #define CONFIG_SYS_SCSI_MAX_LUN 1
  224. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  225. #endif /* CONFIG_SCSI_AHCI */
  226. #endif /* CONFIG_PCI */
  227. #if defined(CONFIG_TSEC_ENET)
  228. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  229. #define CONFIG_TSEC1 1
  230. #define CONFIG_TSEC1_NAME "eTSEC1"
  231. #define CONFIG_TSEC3 1
  232. #define CONFIG_TSEC3_NAME "eTSEC3"
  233. #define CONFIG_PIXIS_SGMII_CMD
  234. #define CONFIG_FSL_SGMII_RISER 1
  235. #define SGMII_RISER_PHY_OFFSET 0x1c
  236. #define TSEC1_PHY_ADDR 0
  237. #define TSEC3_PHY_ADDR 1
  238. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  239. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  240. #define TSEC1_PHYIDX 0
  241. #define TSEC3_PHYIDX 0
  242. #define CONFIG_ETHPRIME "eTSEC1"
  243. #endif /* CONFIG_TSEC_ENET */
  244. /*
  245. * Environment
  246. */
  247. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  248. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  249. /*
  250. * BOOTP options
  251. */
  252. #define CONFIG_BOOTP_BOOTFILESIZE
  253. /*
  254. * USB
  255. */
  256. #ifdef CONFIG_USB_EHCI_HCD
  257. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  258. #define CONFIG_PCI_EHCI_DEVICE 0
  259. #endif
  260. #undef CONFIG_WATCHDOG /* watchdog disabled */
  261. /*
  262. * Miscellaneous configurable options
  263. */
  264. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  265. /*
  266. * For booting Linux, the board info and command line data
  267. * have to be in the first 64 MB of memory, since this is
  268. * the maximum mapped by the Linux kernel during initialization.
  269. */
  270. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  271. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  272. #if defined(CONFIG_CMD_KGDB)
  273. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  274. #endif
  275. /*
  276. * Environment Configuration
  277. */
  278. /* The mac addresses for all ethernet interface */
  279. #if defined(CONFIG_TSEC_ENET)
  280. #define CONFIG_HAS_ETH0
  281. #define CONFIG_HAS_ETH1
  282. #endif
  283. #define CONFIG_IPADDR 192.168.1.251
  284. #define CONFIG_HOSTNAME "8544ds_unknown"
  285. #define CONFIG_ROOTPATH "/nfs/mpc85xx"
  286. #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
  287. #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
  288. #define CONFIG_SERVERIP 192.168.1.1
  289. #define CONFIG_GATEWAYIP 192.168.1.1
  290. #define CONFIG_NETMASK 255.255.0.0
  291. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  292. #define CONFIG_EXTRA_ENV_SETTINGS \
  293. "netdev=eth0\0" \
  294. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  295. "tftpflash=tftpboot $loadaddr $uboot; " \
  296. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  297. " +$filesize; " \
  298. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  299. " +$filesize; " \
  300. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  301. " $filesize; " \
  302. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  303. " +$filesize; " \
  304. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  305. " $filesize\0" \
  306. "consoledev=ttyS0\0" \
  307. "ramdiskaddr=2000000\0" \
  308. "ramdiskfile=8544ds/ramdisk.uboot\0" \
  309. "fdtaddr=1e00000\0" \
  310. "fdtfile=8544ds/mpc8544ds.dtb\0" \
  311. "bdev=sda3\0"
  312. #define CONFIG_NFSBOOTCOMMAND \
  313. "setenv bootargs root=/dev/nfs rw " \
  314. "nfsroot=$serverip:$rootpath " \
  315. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  316. "console=$consoledev,$baudrate $othbootargs;" \
  317. "tftp $loadaddr $bootfile;" \
  318. "tftp $fdtaddr $fdtfile;" \
  319. "bootm $loadaddr - $fdtaddr"
  320. #define CONFIG_RAMBOOTCOMMAND \
  321. "setenv bootargs root=/dev/ram rw " \
  322. "console=$consoledev,$baudrate $othbootargs;" \
  323. "tftp $ramdiskaddr $ramdiskfile;" \
  324. "tftp $loadaddr $bootfile;" \
  325. "tftp $fdtaddr $fdtfile;" \
  326. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  327. #define CONFIG_BOOTCOMMAND \
  328. "setenv bootargs root=/dev/$bdev rw " \
  329. "console=$consoledev,$baudrate $othbootargs;" \
  330. "tftp $loadaddr $bootfile;" \
  331. "tftp $fdtaddr $fdtfile;" \
  332. "bootm $loadaddr - $fdtaddr"
  333. #endif /* __CONFIG_H */