MPC8349ITX.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. */
  5. /*
  6. MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
  7. Memory map:
  8. 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  9. 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  10. 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  11. 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  12. 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  13. 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  14. 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  15. 0xF001_0000-0xF001_FFFF Local bus expansion slot
  16. 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  17. 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  18. 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  19. I2C address list:
  20. Align. Board
  21. Bus Addr Part No. Description Length Location
  22. ----------------------------------------------------------------
  23. I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
  24. I2C1 0x20 PCF8574 I2C Expander 0 U8
  25. I2C1 0x21 PCF8574 I2C Expander 0 U10
  26. I2C1 0x38 PCF8574A I2C Expander 0 U8
  27. I2C1 0x39 PCF8574A I2C Expander 0 U10
  28. I2C1 0x51 (DDR) DDR EEPROM 1 U1
  29. I2C1 0x68 DS1339 RTC 1 U68
  30. Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. #define CONFIG_MISC_INIT_F
  35. /*
  36. * On-board devices
  37. */
  38. #ifdef CONFIG_TARGET_MPC8349ITX
  39. /* The CF card interface on the back of the board */
  40. #define CONFIG_COMPACT_FLASH
  41. #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
  42. #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
  43. #endif
  44. #include <linux/stringify.h>
  45. #define CONFIG_RTC_DS1337
  46. #define CONFIG_SYS_I2C
  47. /*
  48. * Device configurations
  49. */
  50. /* I2C */
  51. #ifdef CONFIG_SYS_I2C
  52. #define CONFIG_SYS_I2C_FSL
  53. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  54. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  55. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  56. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  57. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  58. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  59. #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
  60. #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
  61. #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
  62. #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
  63. #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
  64. #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
  65. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
  66. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
  67. #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
  68. /* Don't probe these addresses: */
  69. #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  70. {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  71. {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  72. {1, CONFIG_SYS_I2C_8574A_ADDR2} }
  73. /* Bit definitions for the 8574[A] I2C expander */
  74. /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
  75. #define I2C_8574_REVISION 0x03
  76. #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
  77. #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
  78. #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
  79. #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
  80. #endif
  81. /* Compact Flash */
  82. #ifdef CONFIG_COMPACT_FLASH
  83. #define CONFIG_SYS_IDE_MAXBUS 1
  84. #define CONFIG_SYS_IDE_MAXDEVICE 1
  85. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  86. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
  87. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
  88. #define CONFIG_SYS_ATA_REG_OFFSET 0
  89. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
  90. #define CONFIG_SYS_ATA_STRIDE 2
  91. /* If a CF card is not inserted, time out quickly */
  92. #define ATA_RESET_TIME 1
  93. #endif
  94. /*
  95. * SATA
  96. */
  97. #ifdef CONFIG_SATA_SIL3114
  98. #define CONFIG_SYS_SATA_MAX_DEVICE 4
  99. #define CONFIG_LBA48
  100. #endif
  101. #ifdef CONFIG_SYS_USB_HOST
  102. /*
  103. * Support USB
  104. */
  105. #define CONFIG_USB_EHCI_FSL
  106. /* Current USB implementation supports the only USB controller,
  107. * so we have to choose between the MPH or the DR ones */
  108. #if 1
  109. #define CONFIG_HAS_FSL_MPH_USB
  110. #else
  111. #define CONFIG_HAS_FSL_DR_USB
  112. #endif
  113. #endif
  114. /*
  115. * DDR Setup
  116. */
  117. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  118. #define CONFIG_SYS_83XX_DDR_USES_CS0
  119. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  120. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  121. #define CONFIG_VERY_BIG_RAM
  122. #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
  123. #ifdef CONFIG_SYS_I2C
  124. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  125. #endif
  126. /* No SPD? Then manually set up DDR parameters */
  127. #ifndef CONFIG_SPD_EEPROM
  128. #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
  129. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  130. | CSCONFIG_ROW_BIT_13 \
  131. | CSCONFIG_COL_BIT_10)
  132. #define CONFIG_SYS_DDR_TIMING_1 0x26242321
  133. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
  134. #endif
  135. /*
  136. *Flash on the Local Bus
  137. */
  138. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  139. #define CONFIG_SYS_FLASH_EMPTY_INFO
  140. /* 127 64KB sectors + 8 8KB sectors per device */
  141. #define CONFIG_SYS_MAX_FLASH_SECT 135
  142. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  143. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  144. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  145. /* The ITX has two flash chips, but the ITX-GP has only one. To support both
  146. boards, we say we have two, but don't display a message if we find only one. */
  147. #define CONFIG_SYS_FLASH_QUIET_TEST
  148. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  149. #define CONFIG_SYS_FLASH_BANKS_LIST \
  150. {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
  151. #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
  152. /* Vitesse 7385 */
  153. #ifdef CONFIG_VSC7385_ENET
  154. #define CONFIG_TSEC2
  155. /* The flash address and size of the VSC7385 firmware image */
  156. #define CONFIG_VSC7385_IMAGE 0xFEFFE000
  157. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  158. #endif
  159. /*
  160. * BRx, ORx, LBLAWBARx, and LBLAWARx
  161. */
  162. /* Vitesse 7385 */
  163. #define CONFIG_SYS_VSC7385_BASE 0xF8000000
  164. #define CONFIG_SYS_LED_BASE 0xF9000000
  165. /* Compact Flash */
  166. #ifdef CONFIG_COMPACT_FLASH
  167. #define CONFIG_SYS_CF_BASE 0xF0000000
  168. #endif
  169. /*
  170. * U-Boot memory configuration
  171. */
  172. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  173. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  174. #define CONFIG_SYS_RAMBOOT
  175. #else
  176. #undef CONFIG_SYS_RAMBOOT
  177. #endif
  178. #define CONFIG_SYS_INIT_RAM_LOCK
  179. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  180. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  181. #define CONFIG_SYS_GBL_DATA_OFFSET \
  182. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  183. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  184. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  185. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  186. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  187. /*
  188. * Serial Port
  189. */
  190. #define CONFIG_SYS_NS16550_SERIAL
  191. #define CONFIG_SYS_NS16550_REG_SIZE 1
  192. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  193. #define CONFIG_SYS_BAUDRATE_TABLE \
  194. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  195. #define CONSOLE ttyS0
  196. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  197. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  198. /*
  199. * PCI
  200. */
  201. #ifdef CONFIG_PCI
  202. #define CONFIG_PCI_INDIRECT_BRIDGE
  203. #define CONFIG_MPC83XX_PCI2
  204. /*
  205. * General PCI
  206. * Addresses are mapped 1-1.
  207. */
  208. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  209. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  210. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  211. #define CONFIG_SYS_PCI1_MMIO_BASE \
  212. (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
  213. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  214. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  215. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  216. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  217. #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
  218. #ifdef CONFIG_MPC83XX_PCI2
  219. #define CONFIG_SYS_PCI2_MEM_BASE \
  220. (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
  221. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  222. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  223. #define CONFIG_SYS_PCI2_MMIO_BASE \
  224. (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
  225. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  226. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  227. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  228. #define CONFIG_SYS_PCI2_IO_PHYS \
  229. (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
  230. #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
  231. #endif
  232. #ifndef CONFIG_PCI_PNP
  233. #define PCI_ENET0_IOADDR 0x00000000
  234. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
  235. #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
  236. #endif
  237. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  238. #endif
  239. /* TSEC */
  240. #ifdef CONFIG_TSEC_ENET
  241. #define CONFIG_TSEC1
  242. #ifdef CONFIG_TSEC1
  243. #define CONFIG_HAS_ETH0
  244. #define CONFIG_TSEC1_NAME "TSEC0"
  245. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  246. #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
  247. #define TSEC1_PHYIDX 0
  248. #define TSEC1_FLAGS TSEC_GIGABIT
  249. #endif
  250. #ifdef CONFIG_TSEC2
  251. #define CONFIG_HAS_ETH1
  252. #define CONFIG_TSEC2_NAME "TSEC1"
  253. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  254. #define TSEC2_PHY_ADDR 4
  255. #define TSEC2_PHYIDX 0
  256. #define TSEC2_FLAGS TSEC_GIGABIT
  257. #endif
  258. #define CONFIG_ETHPRIME "Freescale TSEC"
  259. #endif
  260. /*
  261. * Environment
  262. */
  263. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  264. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  265. /*
  266. * BOOTP options
  267. */
  268. #define CONFIG_BOOTP_BOOTFILESIZE
  269. /* Watchdog */
  270. #undef CONFIG_WATCHDOG /* watchdog disabled */
  271. /*
  272. * Miscellaneous configurable options
  273. */
  274. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  275. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  276. /*
  277. * For booting Linux, the board info and command line data
  278. * have to be in the first 256 MB of memory, since this is
  279. * the maximum mapped by the Linux kernel during initialization.
  280. */
  281. /* Initial Memory map for Linux*/
  282. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  283. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  284. /*
  285. * System performance
  286. */
  287. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  288. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  289. #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
  290. #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
  291. /*
  292. * System IO Config
  293. */
  294. /* Needed for gigabit to work on TSEC 1 */
  295. #define CONFIG_SYS_SICRH SICRH_TSOBI1
  296. /* USB DR as device + USB MPH as host */
  297. #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
  298. #if defined(CONFIG_CMD_KGDB)
  299. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  300. #endif
  301. /*
  302. * Environment Configuration
  303. */
  304. #define CONFIG_NETDEV "eth0"
  305. /* Default path and filenames */
  306. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  307. #define CONFIG_BOOTFILE "uImage"
  308. /* U-Boot image on TFTP server */
  309. #define CONFIG_UBOOTPATH "u-boot.bin"
  310. #ifdef CONFIG_TARGET_MPC8349ITX
  311. #define CONFIG_FDTFILE "mpc8349emitx.dtb"
  312. #else
  313. #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
  314. #endif
  315. #define CONFIG_EXTRA_ENV_SETTINGS \
  316. "console=" __stringify(CONSOLE) "\0" \
  317. "netdev=" CONFIG_NETDEV "\0" \
  318. "uboot=" CONFIG_UBOOTPATH "\0" \
  319. "tftpflash=tftpboot $loadaddr $uboot; " \
  320. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  321. " +$filesize; " \
  322. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  323. " +$filesize; " \
  324. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  325. " $filesize; " \
  326. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  327. " +$filesize; " \
  328. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  329. " $filesize\0" \
  330. "fdtaddr=780000\0" \
  331. "fdtfile=" CONFIG_FDTFILE "\0"
  332. #define CONFIG_NFSBOOTCOMMAND \
  333. "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
  334. " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
  335. " console=$console,$baudrate $othbootargs; " \
  336. "tftp $loadaddr $bootfile;" \
  337. "tftp $fdtaddr $fdtfile;" \
  338. "bootm $loadaddr - $fdtaddr"
  339. #define CONFIG_RAMBOOTCOMMAND \
  340. "setenv bootargs root=/dev/ram rw" \
  341. " console=$console,$baudrate $othbootargs; " \
  342. "tftp $ramdiskaddr $ramdiskfile;" \
  343. "tftp $loadaddr $bootfile;" \
  344. "tftp $fdtaddr $fdtfile;" \
  345. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  346. #endif