MPC8313ERDB_NOR.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
  4. */
  5. /*
  6. * mpc8313epb board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1
  14. #ifndef CONFIG_SYS_MONITOR_BASE
  15. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  16. #endif
  17. #include <linux/stringify.h>
  18. #define CONFIG_PCI_INDIRECT_BRIDGE
  19. /*
  20. * On-board devices
  21. *
  22. * TSEC1 is VSC switch
  23. * TSEC2 is SoC TSEC
  24. */
  25. #define CONFIG_VSC7385_ENET
  26. #define CONFIG_TSEC2
  27. /* Early revs of this board will lock up hard when attempting
  28. * to access the PMC registers, unless a JTAG debugger is
  29. * connected, or some resistor modifications are made.
  30. */
  31. #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  32. /*
  33. * Device configurations
  34. */
  35. /* Vitesse 7385 */
  36. #ifdef CONFIG_VSC7385_ENET
  37. #define CONFIG_TSEC1
  38. /* The flash address and size of the VSC7385 firmware image */
  39. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  40. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  41. #endif
  42. /*
  43. * DDR Setup
  44. */
  45. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  46. /*
  47. * Manually set up DDR parameters, as this board does not
  48. * seem to have the SPD connected to I2C.
  49. */
  50. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  51. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  52. | CSCONFIG_ODT_RD_NEVER \
  53. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  54. | CSCONFIG_ROW_BIT_13 \
  55. | CSCONFIG_COL_BIT_10)
  56. /* 0x80010102 */
  57. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  58. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  59. | (0 << TIMING_CFG0_WRT_SHIFT) \
  60. | (0 << TIMING_CFG0_RRT_SHIFT) \
  61. | (0 << TIMING_CFG0_WWT_SHIFT) \
  62. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  63. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  64. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  65. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  66. /* 0x00220802 */
  67. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  68. | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  69. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  70. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  71. | (10 << TIMING_CFG1_REFREC_SHIFT) \
  72. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  73. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  74. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  75. /* 0x3835a322 */
  76. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  77. | (5 << TIMING_CFG2_CPO_SHIFT) \
  78. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  79. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  80. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  81. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  82. | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  83. /* 0x129048c6 */ /* P9-45,may need tuning */
  84. #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
  85. | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  86. /* 0x05100500 */
  87. #if defined(CONFIG_DDR_2T_TIMING)
  88. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  89. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  90. | SDRAM_CFG_DBW_32 \
  91. | SDRAM_CFG_2T_EN)
  92. /* 0x43088000 */
  93. #else
  94. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  95. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  96. | SDRAM_CFG_DBW_32)
  97. /* 0x43080000 */
  98. #endif
  99. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  100. /* set burst length to 8 for 32-bit data path */
  101. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  102. | (0x0632 << SDRAM_MODE_SD_SHIFT))
  103. /* 0x44480632 */
  104. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  105. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  106. /*0x02000000*/
  107. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  108. | DDRCDR_PZ_NOMZ \
  109. | DDRCDR_NZ_NOMZ \
  110. | DDRCDR_M_ODR)
  111. /*
  112. * FLASH on the Local Bus
  113. */
  114. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  115. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  116. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  117. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  118. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  119. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
  120. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  121. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  122. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
  123. !defined(CONFIG_SPL_BUILD)
  124. #define CONFIG_SYS_RAMBOOT
  125. #endif
  126. #define CONFIG_SYS_INIT_RAM_LOCK 1
  127. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  128. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  129. #define CONFIG_SYS_GBL_DATA_OFFSET \
  130. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  131. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  132. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  133. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  134. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  135. /* drivers/mtd/nand/nand.c */
  136. #define CONFIG_SYS_NAND_BASE 0xE2800000
  137. #define CONFIG_MTD_PARTITION
  138. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  139. #define CONFIG_NAND_FSL_ELBC 1
  140. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  141. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
  142. /* Still needed for spl_minimal.c */
  143. #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
  144. #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
  145. /* local bus write LED / read status buffer (BCSR) mapping */
  146. #define CONFIG_SYS_BCSR_ADDR 0xFA000000
  147. #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
  148. /* map at 0xFA000000 on LCS3 */
  149. /* Vitesse 7385 */
  150. #ifdef CONFIG_VSC7385_ENET
  151. /* VSC7385 Base address on LCS2 */
  152. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  153. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  154. #endif
  155. #define CONFIG_MPC83XX_GPIO 1
  156. /*
  157. * Serial Port
  158. */
  159. #define CONFIG_SYS_NS16550_SERIAL
  160. #define CONFIG_SYS_NS16550_REG_SIZE 1
  161. #define CONFIG_SYS_BAUDRATE_TABLE \
  162. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  163. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  164. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  165. /* I2C */
  166. #define CONFIG_SYS_I2C
  167. #define CONFIG_SYS_I2C_FSL
  168. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  169. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  170. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  171. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  172. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  173. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  174. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  175. /*
  176. * General PCI
  177. * Addresses are mapped 1-1.
  178. */
  179. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  180. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  181. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  182. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  183. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  184. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  185. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  186. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  187. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  188. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  189. /*
  190. * TSEC
  191. */
  192. #define CONFIG_GMII /* MII PHY management */
  193. #ifdef CONFIG_TSEC1
  194. #define CONFIG_HAS_ETH0
  195. #define CONFIG_TSEC1_NAME "TSEC0"
  196. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  197. #define TSEC1_PHY_ADDR 0x1c
  198. #define TSEC1_FLAGS TSEC_GIGABIT
  199. #define TSEC1_PHYIDX 0
  200. #endif
  201. #ifdef CONFIG_TSEC2
  202. #define CONFIG_HAS_ETH1
  203. #define CONFIG_TSEC2_NAME "TSEC1"
  204. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  205. #define TSEC2_PHY_ADDR 4
  206. #define TSEC2_FLAGS TSEC_GIGABIT
  207. #define TSEC2_PHYIDX 0
  208. #endif
  209. /* Options are: TSEC[0-1] */
  210. #define CONFIG_ETHPRIME "TSEC1"
  211. /*
  212. * Configure on-board RTC
  213. */
  214. #define CONFIG_RTC_DS1337
  215. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  216. /*
  217. * Environment
  218. */
  219. #if !defined(CONFIG_SYS_RAMBOOT)
  220. /* Address and size of Redundant Environment Sector */
  221. #endif
  222. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  223. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  224. /*
  225. * BOOTP options
  226. */
  227. #define CONFIG_BOOTP_BOOTFILESIZE
  228. /*
  229. * Miscellaneous configurable options
  230. */
  231. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  232. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  233. /* Boot Argument Buffer Size */
  234. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  235. /*
  236. * For booting Linux, the board info and command line data
  237. * have to be in the first 256 MB of memory, since this is
  238. * the maximum mapped by the Linux kernel during initialization.
  239. */
  240. /* Initial Memory map for Linux*/
  241. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  242. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  243. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  244. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
  245. /* System IO Config */
  246. #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
  247. /* Enable Internal USB Phy and GPIO on LCD Connector */
  248. #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
  249. /*
  250. * Environment Configuration
  251. */
  252. #define CONFIG_NETDEV "eth1"
  253. #define CONFIG_HOSTNAME "mpc8313erdb"
  254. #define CONFIG_ROOTPATH "/nfs/root/path"
  255. #define CONFIG_BOOTFILE "uImage"
  256. /* U-Boot image on TFTP server */
  257. #define CONFIG_UBOOTPATH "u-boot.bin"
  258. #define CONFIG_FDTFILE "mpc8313erdb.dtb"
  259. /* default location for tftp and bootm */
  260. #define CONFIG_LOADADDR 800000
  261. #define CONFIG_EXTRA_ENV_SETTINGS \
  262. "netdev=" CONFIG_NETDEV "\0" \
  263. "ethprime=TSEC1\0" \
  264. "uboot=" CONFIG_UBOOTPATH "\0" \
  265. "tftpflash=tftpboot $loadaddr $uboot; " \
  266. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  267. " +$filesize; " \
  268. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  269. " +$filesize; " \
  270. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  271. " $filesize; " \
  272. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  273. " +$filesize; " \
  274. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  275. " $filesize\0" \
  276. "fdtaddr=780000\0" \
  277. "fdtfile=" CONFIG_FDTFILE "\0" \
  278. "console=ttyS0\0" \
  279. "setbootargs=setenv bootargs " \
  280. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  281. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  282. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  283. "$netdev:off " \
  284. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  285. #define CONFIG_NFSBOOTCOMMAND \
  286. "setenv rootdev /dev/nfs;" \
  287. "run setbootargs;" \
  288. "run setipargs;" \
  289. "tftp $loadaddr $bootfile;" \
  290. "tftp $fdtaddr $fdtfile;" \
  291. "bootm $loadaddr - $fdtaddr"
  292. #define CONFIG_RAMBOOTCOMMAND \
  293. "setenv rootdev /dev/ram;" \
  294. "run setbootargs;" \
  295. "tftp $ramdiskaddr $ramdiskfile;" \
  296. "tftp $loadaddr $bootfile;" \
  297. "tftp $fdtaddr $fdtfile;" \
  298. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  299. #endif /* __CONFIG_H */