MPC8313ERDB_NAND.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
  4. */
  5. /*
  6. * mpc8313epb board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <linux/stringify.h>
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_E300 1
  15. #define CONFIG_SPL_INIT_MINIMAL
  16. #define CONFIG_SPL_FLUSH_IMAGE
  17. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  18. #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  19. #ifdef CONFIG_SPL_BUILD
  20. #define CONFIG_NS16550_MIN_FUNCTIONS
  21. #endif
  22. #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  23. #define CONFIG_SPL_MAX_SIZE (4 * 1024)
  24. #define CONFIG_SPL_PAD_TO 0x4000
  25. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  26. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  27. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  28. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  29. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  30. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  31. #ifdef CONFIG_SPL_BUILD
  32. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  33. #endif
  34. #ifndef CONFIG_SYS_MONITOR_BASE
  35. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  36. #endif
  37. #define CONFIG_PCI_INDIRECT_BRIDGE
  38. /*
  39. * On-board devices
  40. *
  41. * TSEC1 is VSC switch
  42. * TSEC2 is SoC TSEC
  43. */
  44. #define CONFIG_VSC7385_ENET
  45. #define CONFIG_TSEC2
  46. #if !defined(CONFIG_SPL_BUILD)
  47. #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
  48. #endif
  49. /* Early revs of this board will lock up hard when attempting
  50. * to access the PMC registers, unless a JTAG debugger is
  51. * connected, or some resistor modifications are made.
  52. */
  53. #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  54. /*
  55. * Device configurations
  56. */
  57. /* Vitesse 7385 */
  58. #ifdef CONFIG_VSC7385_ENET
  59. #define CONFIG_TSEC1
  60. /* The flash address and size of the VSC7385 firmware image */
  61. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  62. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  63. #endif
  64. /*
  65. * DDR Setup
  66. */
  67. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  68. /*
  69. * Manually set up DDR parameters, as this board does not
  70. * seem to have the SPD connected to I2C.
  71. */
  72. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  73. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  74. | CSCONFIG_ODT_RD_NEVER \
  75. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  76. | CSCONFIG_ROW_BIT_13 \
  77. | CSCONFIG_COL_BIT_10)
  78. /* 0x80010102 */
  79. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  80. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  81. | (0 << TIMING_CFG0_WRT_SHIFT) \
  82. | (0 << TIMING_CFG0_RRT_SHIFT) \
  83. | (0 << TIMING_CFG0_WWT_SHIFT) \
  84. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  85. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  86. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  87. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  88. /* 0x00220802 */
  89. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  90. | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  91. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  92. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  93. | (10 << TIMING_CFG1_REFREC_SHIFT) \
  94. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  95. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  96. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  97. /* 0x3835a322 */
  98. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  99. | (5 << TIMING_CFG2_CPO_SHIFT) \
  100. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  101. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  102. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  103. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  104. | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  105. /* 0x129048c6 */ /* P9-45,may need tuning */
  106. #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
  107. | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  108. /* 0x05100500 */
  109. #if defined(CONFIG_DDR_2T_TIMING)
  110. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  111. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  112. | SDRAM_CFG_DBW_32 \
  113. | SDRAM_CFG_2T_EN)
  114. /* 0x43088000 */
  115. #else
  116. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  117. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  118. | SDRAM_CFG_DBW_32)
  119. /* 0x43080000 */
  120. #endif
  121. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  122. /* set burst length to 8 for 32-bit data path */
  123. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  124. | (0x0632 << SDRAM_MODE_SD_SHIFT))
  125. /* 0x44480632 */
  126. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  127. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  128. /*0x02000000*/
  129. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  130. | DDRCDR_PZ_NOMZ \
  131. | DDRCDR_NZ_NOMZ \
  132. | DDRCDR_M_ODR)
  133. /*
  134. * FLASH on the Local Bus
  135. */
  136. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  137. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  138. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  139. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  140. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
  141. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  142. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  143. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
  144. !defined(CONFIG_SPL_BUILD)
  145. #define CONFIG_SYS_RAMBOOT
  146. #endif
  147. #define CONFIG_SYS_INIT_RAM_LOCK 1
  148. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  149. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  150. #define CONFIG_SYS_GBL_DATA_OFFSET \
  151. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  152. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  153. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  154. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  155. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  156. /* drivers/mtd/nand/raw/nand.c */
  157. #if defined(CONFIG_SPL_BUILD)
  158. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  159. #else
  160. #define CONFIG_SYS_NAND_BASE 0xE2800000
  161. #endif
  162. #define CONFIG_MTD_PARTITION
  163. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  164. #define CONFIG_NAND_FSL_ELBC 1
  165. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  166. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
  167. /* Still needed for spl_minimal.c */
  168. #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
  169. #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
  170. /* local bus write LED / read status buffer (BCSR) mapping */
  171. #define CONFIG_SYS_BCSR_ADDR 0xFA000000
  172. #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
  173. /* map at 0xFA000000 on LCS3 */
  174. /* Vitesse 7385 */
  175. #ifdef CONFIG_VSC7385_ENET
  176. /* VSC7385 Base address on LCS2 */
  177. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  178. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  179. #endif
  180. #define CONFIG_MPC83XX_GPIO 1
  181. /*
  182. * Serial Port
  183. */
  184. #define CONFIG_SYS_NS16550_SERIAL
  185. #define CONFIG_SYS_NS16550_REG_SIZE 1
  186. #define CONFIG_SYS_BAUDRATE_TABLE \
  187. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  188. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  189. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  190. /* I2C */
  191. #define CONFIG_SYS_I2C
  192. #define CONFIG_SYS_I2C_FSL
  193. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  194. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  195. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  196. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  197. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  198. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  199. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  200. /*
  201. * General PCI
  202. * Addresses are mapped 1-1.
  203. */
  204. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  205. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  206. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  207. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  208. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  209. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  210. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  211. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  212. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  213. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  214. /*
  215. * TSEC
  216. */
  217. #define CONFIG_GMII /* MII PHY management */
  218. #ifdef CONFIG_TSEC1
  219. #define CONFIG_HAS_ETH0
  220. #define CONFIG_TSEC1_NAME "TSEC0"
  221. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  222. #define TSEC1_PHY_ADDR 0x1c
  223. #define TSEC1_FLAGS TSEC_GIGABIT
  224. #define TSEC1_PHYIDX 0
  225. #endif
  226. #ifdef CONFIG_TSEC2
  227. #define CONFIG_HAS_ETH1
  228. #define CONFIG_TSEC2_NAME "TSEC1"
  229. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  230. #define TSEC2_PHY_ADDR 4
  231. #define TSEC2_FLAGS TSEC_GIGABIT
  232. #define TSEC2_PHYIDX 0
  233. #endif
  234. /* Options are: TSEC[0-1] */
  235. #define CONFIG_ETHPRIME "TSEC1"
  236. /*
  237. * Configure on-board RTC
  238. */
  239. #define CONFIG_RTC_DS1337
  240. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  241. /*
  242. * Environment
  243. */
  244. #define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
  245. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  246. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  247. /*
  248. * BOOTP options
  249. */
  250. #define CONFIG_BOOTP_BOOTFILESIZE
  251. /*
  252. * Miscellaneous configurable options
  253. */
  254. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  255. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  256. /* Boot Argument Buffer Size */
  257. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  258. /*
  259. * For booting Linux, the board info and command line data
  260. * have to be in the first 256 MB of memory, since this is
  261. * the maximum mapped by the Linux kernel during initialization.
  262. */
  263. /* Initial Memory map for Linux*/
  264. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  265. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  266. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  267. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
  268. /* System IO Config */
  269. #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
  270. /* Enable Internal USB Phy and GPIO on LCD Connector */
  271. #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
  272. /*
  273. * Environment Configuration
  274. */
  275. #define CONFIG_NETDEV "eth1"
  276. #define CONFIG_HOSTNAME "mpc8313erdb"
  277. #define CONFIG_ROOTPATH "/nfs/root/path"
  278. #define CONFIG_BOOTFILE "uImage"
  279. /* U-Boot image on TFTP server */
  280. #define CONFIG_UBOOTPATH "u-boot.bin"
  281. #define CONFIG_FDTFILE "mpc8313erdb.dtb"
  282. /* default location for tftp and bootm */
  283. #define CONFIG_LOADADDR 800000
  284. #define CONFIG_EXTRA_ENV_SETTINGS \
  285. "netdev=" CONFIG_NETDEV "\0" \
  286. "ethprime=TSEC1\0" \
  287. "uboot=" CONFIG_UBOOTPATH "\0" \
  288. "tftpflash=tftpboot $loadaddr $uboot; " \
  289. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  290. " +$filesize; " \
  291. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  292. " +$filesize; " \
  293. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  294. " $filesize; " \
  295. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  296. " +$filesize; " \
  297. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  298. " $filesize\0" \
  299. "fdtaddr=780000\0" \
  300. "fdtfile=" CONFIG_FDTFILE "\0" \
  301. "console=ttyS0\0" \
  302. "setbootargs=setenv bootargs " \
  303. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  304. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  305. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  306. "$netdev:off " \
  307. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  308. #define CONFIG_NFSBOOTCOMMAND \
  309. "setenv rootdev /dev/nfs;" \
  310. "run setbootargs;" \
  311. "run setipargs;" \
  312. "tftp $loadaddr $bootfile;" \
  313. "tftp $fdtaddr $fdtfile;" \
  314. "bootm $loadaddr - $fdtaddr"
  315. #define CONFIG_RAMBOOTCOMMAND \
  316. "setenv rootdev /dev/ram;" \
  317. "run setbootargs;" \
  318. "tftp $ramdiskaddr $ramdiskfile;" \
  319. "tftp $loadaddr $bootfile;" \
  320. "tftp $fdtaddr $fdtfile;" \
  321. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  322. #endif /* __CONFIG_H */