M5485EVB.h 7.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5485 FireEngine board.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5485EVB_H
  12. #define _M5485EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_HW_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  21. #define CONFIG_SLTTMR
  22. #ifdef CONFIG_FSLDMAFEC
  23. # define CONFIG_MII_INIT 1
  24. # define CONFIG_HAS_ETH1
  25. # define CONFIG_SYS_DMA_USE_INTSRAM 1
  26. # define CONFIG_SYS_DISCOVER_PHY
  27. # define CONFIG_SYS_RX_ETH_BUFFER 32
  28. # define CONFIG_SYS_TX_ETH_BUFFER 48
  29. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  30. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  31. # ifndef CONFIG_SYS_DISCOVER_PHY
  32. # define FECDUPLEX FULL
  33. # define FECSPEED _100BASET
  34. # else
  35. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  36. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  37. # endif
  38. # endif /* CONFIG_SYS_DISCOVER_PHY */
  39. # define CONFIG_IPADDR 192.162.1.2
  40. # define CONFIG_NETMASK 255.255.255.0
  41. # define CONFIG_SERVERIP 192.162.1.1
  42. # define CONFIG_GATEWAYIP 192.162.1.1
  43. #endif
  44. #ifdef CONFIG_CMD_USB
  45. # define CONFIG_USB_OHCI_NEW
  46. /*# define CONFIG_PCI_OHCI*/
  47. # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
  48. # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  49. # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
  50. # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  51. #endif
  52. /* I2C */
  53. #define CONFIG_SYS_I2C
  54. #define CONFIG_SYS_I2C_FSL
  55. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  56. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  57. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
  58. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  59. /* PCI */
  60. #ifdef CONFIG_CMD_PCI
  61. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  62. #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
  63. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
  64. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
  65. #define CONFIG_SYS_PCI_IO_BUS 0x71000000
  66. #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
  67. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
  68. #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
  69. #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
  70. #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
  71. #endif
  72. #define CONFIG_UDP_CHECKSUM
  73. #define CONFIG_HOSTNAME "M548xEVB"
  74. #define CONFIG_EXTRA_ENV_SETTINGS \
  75. "netdev=eth0\0" \
  76. "loadaddr=10000\0" \
  77. "u-boot=u-boot.bin\0" \
  78. "load=tftp ${loadaddr) ${u-boot}\0" \
  79. "upd=run load; run prog\0" \
  80. "prog=prot off bank 1;" \
  81. "era ff800000 ff83ffff;" \
  82. "cp.b ${loadaddr} ff800000 ${filesize};"\
  83. "save\0" \
  84. ""
  85. #define CONFIG_PRAM 512 /* 512 KB */
  86. #define CONFIG_SYS_LOAD_ADDR 0x00010000
  87. #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
  88. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
  89. #define CONFIG_SYS_MBAR 0xF0000000
  90. #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
  91. #define CONFIG_SYS_INTSRAMSZ 0x8000
  92. /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
  93. /*
  94. * Low Level Configuration Settings
  95. * (address mappings, register initial values, etc.)
  96. * You should know what you are doing if you make changes here.
  97. */
  98. /*-----------------------------------------------------------------------
  99. * Definitions for initial stack pointer and data area (in DPRAM)
  100. */
  101. #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
  102. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
  103. #define CONFIG_SYS_INIT_RAM_CTRL 0x21
  104. #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  105. #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
  106. #define CONFIG_SYS_INIT_RAM1_CTRL 0x21
  107. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  108. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  109. /*-----------------------------------------------------------------------
  110. * Start addresses for the final memory configuration
  111. * (Set up by the startup code)
  112. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  113. */
  114. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  115. #define CONFIG_SYS_SDRAM_CFG1 0x73711630
  116. #define CONFIG_SYS_SDRAM_CFG2 0x46770000
  117. #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
  118. #define CONFIG_SYS_SDRAM_EMOD 0x40010000
  119. #define CONFIG_SYS_SDRAM_MODE 0x018D0000
  120. #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
  121. #ifdef CONFIG_SYS_DRAMSZ1
  122. # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
  123. #else
  124. # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
  125. #endif
  126. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  127. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  128. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  129. /* Reserve 256 kB for malloc() */
  130. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  131. /*
  132. * For booting Linux, the board info and command line data
  133. * have to be in the first 8 MB of memory, since this is
  134. * the maximum mapped by the Linux kernel during initialization ??
  135. */
  136. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  137. /*-----------------------------------------------------------------------
  138. * FLASH organization
  139. */
  140. #ifdef CONFIG_SYS_FLASH_CFI
  141. # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  142. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  143. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  144. #ifdef CONFIG_SYS_NOR1SZ
  145. # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  146. # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
  147. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
  148. #else
  149. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  150. # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
  151. #endif
  152. #endif
  153. /* Configuration for environment
  154. * Environment is not embedded in u-boot. First time runing may have env
  155. * crc error warning if there is no correct environment on the flash.
  156. */
  157. /*-----------------------------------------------------------------------
  158. * Cache Configuration
  159. */
  160. #define CONFIG_SYS_CACHELINE_SIZE 16
  161. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  162. CONFIG_SYS_INIT_RAM_SIZE - 8)
  163. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  164. CONFIG_SYS_INIT_RAM_SIZE - 4)
  165. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
  166. CF_CACR_IDCM)
  167. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  168. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  169. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  170. CF_ACR_EN | CF_ACR_SM_ALL)
  171. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
  172. CF_CACR_IEC | CF_CACR_ICINVA)
  173. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  174. CF_CACR_DEC | CF_CACR_DDCM_P | \
  175. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  176. /*-----------------------------------------------------------------------
  177. * Chipselect bank definitions
  178. */
  179. /*
  180. * CS0 - NOR Flash 1, 2, 4, or 8MB
  181. * CS1 - NOR Flash
  182. * CS2 - Available
  183. * CS3 - Available
  184. * CS4 - Available
  185. * CS5 - Available
  186. */
  187. #define CONFIG_SYS_CS0_BASE 0xFF800000
  188. #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
  189. #define CONFIG_SYS_CS0_CTRL 0x00101980
  190. #ifdef CONFIG_SYS_NOR1SZ
  191. #define CONFIG_SYS_CS1_BASE 0xE0000000
  192. #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
  193. #define CONFIG_SYS_CS1_CTRL 0x00101D80
  194. #endif
  195. #endif /* _M5485EVB_H */