M5475EVB.h 7.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5475 board.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5475EVB_H
  12. #define _M5475EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_HW_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  21. #define CONFIG_SLTTMR
  22. #ifdef CONFIG_FSLDMAFEC
  23. # define CONFIG_MII_INIT 1
  24. # define CONFIG_HAS_ETH1
  25. # define CONFIG_SYS_DMA_USE_INTSRAM 1
  26. # define CONFIG_SYS_DISCOVER_PHY
  27. # define CONFIG_SYS_RX_ETH_BUFFER 32
  28. # define CONFIG_SYS_TX_ETH_BUFFER 48
  29. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  30. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  31. # ifndef CONFIG_SYS_DISCOVER_PHY
  32. # define FECDUPLEX FULL
  33. # define FECSPEED _100BASET
  34. # else
  35. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  36. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  37. # endif
  38. # endif /* CONFIG_SYS_DISCOVER_PHY */
  39. # define CONFIG_IPADDR 192.162.1.2
  40. # define CONFIG_NETMASK 255.255.255.0
  41. # define CONFIG_SERVERIP 192.162.1.1
  42. # define CONFIG_GATEWAYIP 192.162.1.1
  43. #endif
  44. #ifdef CONFIG_CMD_USB
  45. # define CONFIG_USB_OHCI_NEW
  46. # define CONFIG_PCI_OHCI
  47. # undef CONFIG_SYS_USB_OHCI_BOARD_INIT
  48. # undef CONFIG_SYS_USB_OHCI_CPU_INIT
  49. # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  50. # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
  51. # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  52. #endif
  53. /* I2C */
  54. #define CONFIG_SYS_I2C
  55. #define CONFIG_SYS_I2C_FSL
  56. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  57. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  58. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
  59. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  60. /* PCI */
  61. #ifdef CONFIG_CMD_PCI
  62. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  63. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
  64. #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
  65. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
  66. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
  67. #define CONFIG_SYS_PCI_IO_BUS 0x71000000
  68. #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
  69. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
  70. #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
  71. #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
  72. #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
  73. #endif
  74. #define CONFIG_UDP_CHECKSUM
  75. #ifdef CONFIG_MCFFEC
  76. # define CONFIG_IPADDR 192.162.1.2
  77. # define CONFIG_NETMASK 255.255.255.0
  78. # define CONFIG_SERVERIP 192.162.1.1
  79. # define CONFIG_GATEWAYIP 192.162.1.1
  80. #endif /* FEC_ENET */
  81. #define CONFIG_HOSTNAME "M547xEVB"
  82. #define CONFIG_EXTRA_ENV_SETTINGS \
  83. "netdev=eth0\0" \
  84. "loadaddr=10000\0" \
  85. "u-boot=u-boot.bin\0" \
  86. "load=tftp ${loadaddr) ${u-boot}\0" \
  87. "upd=run load; run prog\0" \
  88. "prog=prot off bank 1;" \
  89. "era ff800000 ff83ffff;" \
  90. "cp.b ${loadaddr} ff800000 ${filesize};"\
  91. "save\0" \
  92. ""
  93. #define CONFIG_PRAM 512 /* 512 KB */
  94. #define CONFIG_SYS_LOAD_ADDR 0x00010000
  95. #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
  96. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
  97. #define CONFIG_SYS_MBAR 0xF0000000
  98. #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
  99. #define CONFIG_SYS_INTSRAMSZ 0x8000
  100. /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
  101. /*
  102. * Low Level Configuration Settings
  103. * (address mappings, register initial values, etc.)
  104. * You should know what you are doing if you make changes here.
  105. */
  106. /*-----------------------------------------------------------------------
  107. * Definitions for initial stack pointer and data area (in DPRAM)
  108. */
  109. #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
  110. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
  111. #define CONFIG_SYS_INIT_RAM_CTRL 0x21
  112. #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  113. #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
  114. #define CONFIG_SYS_INIT_RAM1_CTRL 0x21
  115. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  116. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  117. /*-----------------------------------------------------------------------
  118. * Start addresses for the final memory configuration
  119. * (Set up by the startup code)
  120. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  121. */
  122. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  123. #define CONFIG_SYS_SDRAM_CFG1 0x73711630
  124. #define CONFIG_SYS_SDRAM_CFG2 0x46770000
  125. #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
  126. #define CONFIG_SYS_SDRAM_EMOD 0x40010000
  127. #define CONFIG_SYS_SDRAM_MODE 0x018D0000
  128. #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
  129. #ifdef CONFIG_SYS_DRAMSZ1
  130. # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
  131. #else
  132. # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
  133. #endif
  134. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  135. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  136. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  137. /* Reserve 256 kB for malloc() */
  138. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  139. /*
  140. * For booting Linux, the board info and command line data
  141. * have to be in the first 8 MB of memory, since this is
  142. * the maximum mapped by the Linux kernel during initialization ??
  143. */
  144. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  145. /*-----------------------------------------------------------------------
  146. * FLASH organization
  147. */
  148. #ifdef CONFIG_SYS_FLASH_CFI
  149. # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  150. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  151. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  152. #ifdef CONFIG_SYS_NOR1SZ
  153. # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  154. # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
  155. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
  156. #else
  157. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  158. # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
  159. #endif
  160. #endif
  161. /* Configuration for environment
  162. * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
  163. * First time runing may have env crc error warning if there is
  164. * no correct environment on the flash.
  165. */
  166. /*-----------------------------------------------------------------------
  167. * Cache Configuration
  168. */
  169. #define CONFIG_SYS_CACHELINE_SIZE 16
  170. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  171. CONFIG_SYS_INIT_RAM_SIZE - 8)
  172. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  173. CONFIG_SYS_INIT_RAM_SIZE - 4)
  174. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
  175. CF_CACR_IDCM)
  176. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  177. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  178. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  179. CF_ACR_EN | CF_ACR_SM_ALL)
  180. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
  181. CF_CACR_IEC | CF_CACR_ICINVA)
  182. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  183. CF_CACR_DEC | CF_CACR_DDCM_P | \
  184. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  185. /*-----------------------------------------------------------------------
  186. * Chipselect bank definitions
  187. */
  188. /*
  189. * CS0 - NOR Flash 1, 2, 4, or 8MB
  190. * CS1 - NOR Flash
  191. * CS2 - Available
  192. * CS3 - Available
  193. * CS4 - Available
  194. * CS5 - Available
  195. */
  196. #define CONFIG_SYS_CS0_BASE 0xFF800000
  197. #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
  198. #define CONFIG_SYS_CS0_CTRL 0x00101980
  199. #ifdef CONFIG_SYS_NOR1SZ
  200. #define CONFIG_SYS_CS1_BASE 0xE0000000
  201. #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
  202. #define CONFIG_SYS_CS1_CTRL 0x00101D80
  203. #endif
  204. #endif /* _M5475EVB_H */