M54455EVB.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF54455 EVB board.
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M54455EVB_H
  12. #define _M54455EVB_H
  13. #include <linux/stringify.h>
  14. /*
  15. * High Level Configuration Options
  16. * (easy to change)
  17. */
  18. #define CONFIG_M54455EVB /* M54455EVB board */
  19. #define CONFIG_MCFUART
  20. #define CONFIG_SYS_UART_PORT (0)
  21. #define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
  22. #undef CONFIG_WATCHDOG
  23. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  24. /*
  25. * BOOTP options
  26. */
  27. #define CONFIG_BOOTP_BOOTFILESIZE
  28. /* Network configuration */
  29. #ifdef CONFIG_MCFFEC
  30. # define CONFIG_MII_INIT 1
  31. # define CONFIG_SYS_DISCOVER_PHY
  32. # define CONFIG_SYS_RX_ETH_BUFFER 8
  33. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  34. # define CONFIG_HAS_ETH1
  35. # define CONFIG_ETHPRIME "FEC0"
  36. # define CONFIG_IPADDR 192.162.1.2
  37. # define CONFIG_NETMASK 255.255.255.0
  38. # define CONFIG_SERVERIP 192.162.1.1
  39. # define CONFIG_GATEWAYIP 192.162.1.1
  40. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  41. # ifndef CONFIG_SYS_DISCOVER_PHY
  42. # define FECDUPLEX FULL
  43. # define FECSPEED _100BASET
  44. # else
  45. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  46. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  47. # endif
  48. # endif /* CONFIG_SYS_DISCOVER_PHY */
  49. #endif
  50. #define CONFIG_HOSTNAME "M54455EVB"
  51. #ifdef CONFIG_SYS_STMICRO_BOOT
  52. /* ST Micro serial flash */
  53. #define CONFIG_SYS_LOAD_ADDR2 0x40010013
  54. #define CONFIG_EXTRA_ENV_SETTINGS \
  55. "netdev=eth0\0" \
  56. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  57. "loadaddr=0x40010000\0" \
  58. "sbfhdr=sbfhdr.bin\0" \
  59. "uboot=u-boot.bin\0" \
  60. "load=tftp ${loadaddr} ${sbfhdr};" \
  61. "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
  62. "upd=run load; run prog\0" \
  63. "prog=sf probe 0:1 1000000 3;" \
  64. "sf erase 0 30000;" \
  65. "sf write ${loadaddr} 0 0x30000;" \
  66. "save\0" \
  67. ""
  68. #else
  69. /* Atmel and Intel */
  70. #ifdef CONFIG_SYS_ATMEL_BOOT
  71. # define CONFIG_SYS_UBOOT_END 0x0403FFFF
  72. #elif defined(CONFIG_SYS_INTEL_BOOT)
  73. # define CONFIG_SYS_UBOOT_END 0x3FFFF
  74. #endif
  75. #define CONFIG_EXTRA_ENV_SETTINGS \
  76. "netdev=eth0\0" \
  77. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  78. "loadaddr=0x40010000\0" \
  79. "uboot=u-boot.bin\0" \
  80. "load=tftp ${loadaddr} ${uboot}\0" \
  81. "upd=run load; run prog\0" \
  82. "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
  83. " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
  84. "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
  85. __stringify(CONFIG_SYS_UBOOT_END) ";" \
  86. "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
  87. " ${filesize}; save\0" \
  88. ""
  89. #endif
  90. /* ATA configuration */
  91. #define CONFIG_IDE_RESET 1
  92. #define CONFIG_IDE_PREINIT 1
  93. #define CONFIG_ATAPI
  94. #undef CONFIG_LBA48
  95. #define CONFIG_SYS_IDE_MAXBUS 1
  96. #define CONFIG_SYS_IDE_MAXDEVICE 2
  97. #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
  98. #define CONFIG_SYS_ATA_IDE0_OFFSET 0
  99. #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
  100. #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
  101. #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
  102. #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
  103. /* Realtime clock */
  104. #define CONFIG_MCFRTC
  105. #undef RTC_DEBUG
  106. #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
  107. /* Timer */
  108. #define CONFIG_MCFTMR
  109. /* I2c */
  110. #define CONFIG_SYS_I2C
  111. #define CONFIG_SYS_I2C_FSL
  112. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  113. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  114. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  115. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  116. /* DSPI and Serial Flash */
  117. #define CONFIG_CF_DSPI
  118. #define CONFIG_SYS_SBFHDR_SIZE 0x13
  119. /* PCI */
  120. #ifdef CONFIG_CMD_PCI
  121. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  122. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
  123. #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
  124. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
  125. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
  126. #define CONFIG_SYS_PCI_IO_BUS 0xB1000000
  127. #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
  128. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
  129. #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
  130. #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
  131. #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
  132. #endif
  133. /* FPGA - Spartan 2 */
  134. /* experiment
  135. #define CONFIG_FPGA_COUNT 1
  136. #define CONFIG_SYS_FPGA_PROG_FEEDBACK
  137. #define CONFIG_SYS_FPGA_CHECK_CTRLC
  138. */
  139. /* Input, PCI, Flexbus, and VCO */
  140. #define CONFIG_EXTRA_CLOCK
  141. #define CONFIG_PRAM 2048 /* 2048 KB */
  142. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  143. #define CONFIG_SYS_MBAR 0xFC000000
  144. /*
  145. * Low Level Configuration Settings
  146. * (address mappings, register initial values, etc.)
  147. * You should know what you are doing if you make changes here.
  148. */
  149. /*-----------------------------------------------------------------------
  150. * Definitions for initial stack pointer and data area (in DPRAM)
  151. */
  152. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  153. #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
  154. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  155. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
  156. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  157. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  158. /*-----------------------------------------------------------------------
  159. * Start addresses for the final memory configuration
  160. * (Set up by the startup code)
  161. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  162. */
  163. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  164. #define CONFIG_SYS_SDRAM_BASE1 0x48000000
  165. #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
  166. #define CONFIG_SYS_SDRAM_CFG1 0x65311610
  167. #define CONFIG_SYS_SDRAM_CFG2 0x59670000
  168. #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
  169. #define CONFIG_SYS_SDRAM_EMOD 0x40010000
  170. #define CONFIG_SYS_SDRAM_MODE 0x00010033
  171. #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
  172. #ifdef CONFIG_CF_SBF
  173. # define CONFIG_SERIAL_BOOT
  174. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
  175. #else
  176. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  177. #endif
  178. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  179. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  180. /* Reserve 256 kB for malloc() */
  181. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  182. /*
  183. * For booting Linux, the board info and command line data
  184. * have to be in the first 8 MB of memory, since this is
  185. * the maximum mapped by the Linux kernel during initialization ??
  186. */
  187. /* Initial Memory map for Linux */
  188. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  189. /*
  190. * Configuration for environment
  191. * Environment is not embedded in u-boot. First time runing may have env
  192. * crc error warning if there is no correct environment on the flash.
  193. */
  194. /*-----------------------------------------------------------------------
  195. * FLASH organization
  196. */
  197. #ifdef CONFIG_SYS_STMICRO_BOOT
  198. # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  199. # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
  200. #endif
  201. #ifdef CONFIG_SYS_ATMEL_BOOT
  202. # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  203. # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
  204. # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
  205. #endif
  206. #ifdef CONFIG_SYS_INTEL_BOOT
  207. # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  208. # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
  209. # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
  210. #endif
  211. #ifdef CONFIG_SYS_FLASH_CFI
  212. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  213. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  214. # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  215. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  216. # define CONFIG_SYS_FLASH_CHECKSUM
  217. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
  218. # define CONFIG_FLASH_CFI_LEGACY
  219. #ifdef CONFIG_FLASH_CFI_LEGACY
  220. # define CONFIG_SYS_ATMEL_REGION 4
  221. # define CONFIG_SYS_ATMEL_TOTALSECT 11
  222. # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
  223. # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
  224. #endif
  225. #endif
  226. /*
  227. * This is setting for JFFS2 support in u-boot.
  228. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  229. */
  230. #ifdef CONFIG_CMD_JFFS2
  231. #ifdef CF_STMICRO_BOOT
  232. # define CONFIG_JFFS2_DEV "nor1"
  233. # define CONFIG_JFFS2_PART_SIZE 0x01000000
  234. # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
  235. #endif
  236. #ifdef CONFIG_SYS_ATMEL_BOOT
  237. # define CONFIG_JFFS2_DEV "nor1"
  238. # define CONFIG_JFFS2_PART_SIZE 0x01000000
  239. # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
  240. #endif
  241. #ifdef CONFIG_SYS_INTEL_BOOT
  242. # define CONFIG_JFFS2_DEV "nor0"
  243. # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
  244. # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
  245. #endif
  246. #endif
  247. /*-----------------------------------------------------------------------
  248. * Cache Configuration
  249. */
  250. #define CONFIG_SYS_CACHELINE_SIZE 16
  251. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  252. CONFIG_SYS_INIT_RAM_SIZE - 8)
  253. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  254. CONFIG_SYS_INIT_RAM_SIZE - 4)
  255. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
  256. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  257. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  258. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  259. CF_ACR_EN | CF_ACR_SM_ALL)
  260. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
  261. CF_CACR_ICINVA | CF_CACR_EUSP)
  262. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  263. CF_CACR_DEC | CF_CACR_DDCM_P | \
  264. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  265. /*-----------------------------------------------------------------------
  266. * Memory bank definitions
  267. */
  268. /*
  269. * CS0 - NOR Flash 1, 2, 4, or 8MB
  270. * CS1 - CompactFlash and registers
  271. * CS2 - CPLD
  272. * CS3 - FPGA
  273. * CS4 - Available
  274. * CS5 - Available
  275. */
  276. #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
  277. /* Atmel Flash */
  278. #define CONFIG_SYS_CS0_BASE 0x04000000
  279. #define CONFIG_SYS_CS0_MASK 0x00070001
  280. #define CONFIG_SYS_CS0_CTRL 0x00001140
  281. /* Intel Flash */
  282. #define CONFIG_SYS_CS1_BASE 0x00000000
  283. #define CONFIG_SYS_CS1_MASK 0x01FF0001
  284. #define CONFIG_SYS_CS1_CTRL 0x00000D60
  285. #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
  286. #else
  287. /* Intel Flash */
  288. #define CONFIG_SYS_CS0_BASE 0x00000000
  289. #define CONFIG_SYS_CS0_MASK 0x01FF0001
  290. #define CONFIG_SYS_CS0_CTRL 0x00000D60
  291. /* Atmel Flash */
  292. #define CONFIG_SYS_CS1_BASE 0x04000000
  293. #define CONFIG_SYS_CS1_MASK 0x00070001
  294. #define CONFIG_SYS_CS1_CTRL 0x00001140
  295. #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
  296. #endif
  297. /* CPLD */
  298. #define CONFIG_SYS_CS2_BASE 0x08000000
  299. #define CONFIG_SYS_CS2_MASK 0x00070001
  300. #define CONFIG_SYS_CS2_CTRL 0x003f1140
  301. /* FPGA */
  302. #define CONFIG_SYS_CS3_BASE 0x09000000
  303. #define CONFIG_SYS_CS3_MASK 0x00070001
  304. #define CONFIG_SYS_CS3_CTRL 0x00000020
  305. #endif /* _M54455EVB_H */