M54451EVB.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF54451 EVB board.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M54451EVB_H
  12. #define _M54451EVB_H
  13. #include <linux/stringify.h>
  14. /*
  15. * High Level Configuration Options
  16. * (easy to change)
  17. */
  18. #define CONFIG_M54451EVB /* M54451EVB board */
  19. #define CONFIG_MCFUART
  20. #define CONFIG_SYS_UART_PORT (0)
  21. #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
  22. #undef CONFIG_WATCHDOG
  23. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  24. /*
  25. * BOOTP options
  26. */
  27. #define CONFIG_BOOTP_BOOTFILESIZE
  28. /* Network configuration */
  29. #ifdef CONFIG_MCFFEC
  30. # define CONFIG_MII_INIT 1
  31. # define CONFIG_SYS_DISCOVER_PHY
  32. # define CONFIG_SYS_RX_ETH_BUFFER 8
  33. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  34. # define CONFIG_ETHPRIME "FEC0"
  35. # define CONFIG_IPADDR 192.162.1.2
  36. # define CONFIG_NETMASK 255.255.255.0
  37. # define CONFIG_SERVERIP 192.162.1.1
  38. # define CONFIG_GATEWAYIP 192.162.1.1
  39. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  40. # ifndef CONFIG_SYS_DISCOVER_PHY
  41. # define FECDUPLEX FULL
  42. # define FECSPEED _100BASET
  43. # else
  44. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  46. # endif
  47. # endif /* CONFIG_SYS_DISCOVER_PHY */
  48. #endif
  49. #define CONFIG_HOSTNAME "M54451EVB"
  50. #ifdef CONFIG_SYS_STMICRO_BOOT
  51. /* ST Micro serial flash */
  52. #define CONFIG_SYS_LOAD_ADDR2 0x40010007
  53. #define CONFIG_EXTRA_ENV_SETTINGS \
  54. "netdev=eth0\0" \
  55. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  56. "loadaddr=0x40010000\0" \
  57. "sbfhdr=sbfhdr.bin\0" \
  58. "uboot=u-boot.bin\0" \
  59. "load=tftp ${loadaddr} ${sbfhdr};" \
  60. "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
  61. "upd=run load; run prog\0" \
  62. "prog=sf probe 0:1 1000000 3;" \
  63. "sf erase 0 30000;" \
  64. "sf write ${loadaddr} 0 30000;" \
  65. "save\0" \
  66. ""
  67. #else
  68. #define CONFIG_SYS_UBOOT_END 0x3FFFF
  69. #define CONFIG_EXTRA_ENV_SETTINGS \
  70. "netdev=eth0\0" \
  71. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  72. "loadaddr=40010000\0" \
  73. "u-boot=u-boot.bin\0" \
  74. "load=tftp ${loadaddr) ${u-boot}\0" \
  75. "upd=run load; run prog\0" \
  76. "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
  77. "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
  78. "cp.b ${loadaddr} 0 ${filesize};" \
  79. "save\0" \
  80. ""
  81. #endif
  82. /* Realtime clock */
  83. #define CONFIG_MCFRTC
  84. #undef RTC_DEBUG
  85. #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
  86. /* Timer */
  87. #define CONFIG_MCFTMR
  88. /* I2c */
  89. #define CONFIG_SYS_I2C
  90. #define CONFIG_SYS_I2C_FSL
  91. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  92. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  93. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  94. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  95. /* DSPI and Serial Flash */
  96. #define CONFIG_CF_DSPI
  97. #define CONFIG_SERIAL_FLASH
  98. #define CONFIG_SYS_SBFHDR_SIZE 0x7
  99. /* Input, PCI, Flexbus, and VCO */
  100. #define CONFIG_EXTRA_CLOCK
  101. #define CONFIG_PRAM 2048 /* 2048 KB */
  102. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  103. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  104. #define CONFIG_SYS_MBAR 0xFC000000
  105. /*
  106. * Low Level Configuration Settings
  107. * (address mappings, register initial values, etc.)
  108. * You should know what you are doing if you make changes here.
  109. */
  110. /*-----------------------------------------------------------------------
  111. * Definitions for initial stack pointer and data area (in DPRAM)
  112. */
  113. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  114. #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
  115. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  116. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
  117. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  118. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  119. /*-----------------------------------------------------------------------
  120. * Start addresses for the final memory configuration
  121. * (Set up by the startup code)
  122. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  123. */
  124. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  125. #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
  126. #define CONFIG_SYS_SDRAM_CFG1 0x33633F30
  127. #define CONFIG_SYS_SDRAM_CFG2 0x57670000
  128. #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
  129. #define CONFIG_SYS_SDRAM_EMOD 0x80810000
  130. #define CONFIG_SYS_SDRAM_MODE 0x008D0000
  131. #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
  132. #ifdef CONFIG_CF_SBF
  133. # define CONFIG_SERIAL_BOOT
  134. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
  135. #else
  136. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  137. #endif
  138. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  139. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  140. /* Reserve 256 kB for malloc() */
  141. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  142. /*
  143. * For booting Linux, the board info and command line data
  144. * have to be in the first 8 MB of memory, since this is
  145. * the maximum mapped by the Linux kernel during initialization ??
  146. */
  147. /* Initial Memory map for Linux */
  148. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  149. /* Configuration for environment
  150. * Environment is not embedded in u-boot. First time runing may have env
  151. * crc error warning if there is no correct environment on the flash.
  152. */
  153. /* FLASH organization */
  154. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  155. #ifdef CONFIG_SYS_FLASH_CFI
  156. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  157. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  158. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  159. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  160. # define CONFIG_SYS_FLASH_CHECKSUM
  161. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
  162. #endif
  163. /*
  164. * This is setting for JFFS2 support in u-boot.
  165. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  166. */
  167. #ifdef CONFIG_CMD_JFFS2
  168. # define CONFIG_JFFS2_DEV "nor0"
  169. # define CONFIG_JFFS2_PART_SIZE 0x01000000
  170. # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
  171. #endif
  172. /* Cache Configuration */
  173. #define CONFIG_SYS_CACHELINE_SIZE 16
  174. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  175. CONFIG_SYS_INIT_RAM_SIZE - 8)
  176. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  177. CONFIG_SYS_INIT_RAM_SIZE - 4)
  178. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
  179. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  180. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  181. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  182. CF_ACR_EN | CF_ACR_SM_ALL)
  183. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
  184. CF_CACR_ICINVA | CF_CACR_EUSP)
  185. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  186. CF_CACR_DEC | CF_CACR_DDCM_P | \
  187. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  188. /*-----------------------------------------------------------------------
  189. * Memory bank definitions
  190. */
  191. /*
  192. * CS0 - NOR Flash 16MB
  193. * CS1 - Available
  194. * CS2 - Available
  195. * CS3 - Available
  196. * CS4 - Available
  197. * CS5 - Available
  198. */
  199. /* Flash */
  200. #define CONFIG_SYS_CS0_BASE 0x00000000
  201. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  202. #define CONFIG_SYS_CS0_CTRL 0x00004D80
  203. #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
  204. #endif /* _M54451EVB_H */