M54418TWR.h 7.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF54418 TWR board.
  4. *
  5. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M54418TWR_H
  12. #define _M54418TWR_H
  13. #include <linux/stringify.h>
  14. /*
  15. * High Level Configuration Options
  16. * (easy to change)
  17. */
  18. #define CONFIG_MCFUART
  19. #define CONFIG_SYS_UART_PORT (0)
  20. #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  21. #define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
  22. #undef CONFIG_WATCHDOG
  23. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  24. /*
  25. * BOOTP options
  26. */
  27. #define CONFIG_BOOTP_BOOTFILESIZE
  28. /*
  29. * NAND FLASH
  30. */
  31. #ifdef CONFIG_CMD_NAND
  32. #define CONFIG_JFFS2_NAND
  33. #define CONFIG_NAND_FSL_NFC
  34. #define CONFIG_SYS_NAND_BASE 0xFC0FC000
  35. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  36. #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  37. #define CONFIG_SYS_NAND_SELECT_DEVICE
  38. #endif
  39. /* Network configuration */
  40. #ifdef CONFIG_MCFFEC
  41. #define CONFIG_MII_INIT 1
  42. #define CONFIG_SYS_DISCOVER_PHY
  43. #define CONFIG_SYS_RX_ETH_BUFFER 2
  44. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45. #define CONFIG_SYS_TX_ETH_BUFFER 2
  46. #define CONFIG_HAS_ETH1
  47. #define CONFIG_ETHPRIME "FEC0"
  48. #define CONFIG_IPADDR 192.168.1.2
  49. #define CONFIG_NETMASK 255.255.255.0
  50. #define CONFIG_SERVERIP 192.168.1.1
  51. #define CONFIG_GATEWAYIP 192.168.1.1
  52. #define CONFIG_SYS_FEC_BUF_USE_SRAM
  53. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  54. #ifndef CONFIG_SYS_DISCOVER_PHY
  55. #define FECDUPLEX FULL
  56. #define FECSPEED _100BASET
  57. #define LINKSTATUS 1
  58. #else
  59. #define LINKSTATUS 0
  60. #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  61. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  62. #endif
  63. #endif /* CONFIG_SYS_DISCOVER_PHY */
  64. #endif
  65. #define CONFIG_HOSTNAME "M54418TWR"
  66. #if defined(CONFIG_CF_SBF)
  67. /* ST Micro serial flash */
  68. #define CONFIG_SYS_LOAD_ADDR2 0x40010007
  69. #define CONFIG_EXTRA_ENV_SETTINGS \
  70. "netdev=eth0\0" \
  71. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  72. "loadaddr=0x40010000\0" \
  73. "sbfhdr=sbfhdr.bin\0" \
  74. "uboot=u-boot.bin\0" \
  75. "load=tftp ${loadaddr} ${sbfhdr};" \
  76. "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
  77. "upd=run load; run prog\0" \
  78. "prog=sf probe 0:1 1000000 3;" \
  79. "sf erase 0 40000;" \
  80. "sf write ${loadaddr} 0 40000;" \
  81. "save\0" \
  82. ""
  83. #elif defined(CONFIG_SYS_NAND_BOOT)
  84. #define CONFIG_EXTRA_ENV_SETTINGS \
  85. "netdev=eth0\0" \
  86. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  87. "loadaddr=0x40010000\0" \
  88. "u-boot=u-boot.bin\0" \
  89. "load=tftp ${loadaddr} ${u-boot};\0" \
  90. "upd=run load; run prog\0" \
  91. "prog=nand device 0;" \
  92. "nand erase 0 40000;" \
  93. "nb_update ${loadaddr} ${filesize};" \
  94. "save\0" \
  95. ""
  96. #else
  97. #define CONFIG_SYS_UBOOT_END 0x3FFFF
  98. #define CONFIG_EXTRA_ENV_SETTINGS \
  99. "netdev=eth0\0" \
  100. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  101. "loadaddr=40010000\0" \
  102. "u-boot=u-boot.bin\0" \
  103. "load=tftp ${loadaddr) ${u-boot}\0" \
  104. "upd=run load; run prog\0" \
  105. "prog=prot off mram" " ;" \
  106. "cp.b ${loadaddr} 0 ${filesize};" \
  107. "save\0" \
  108. ""
  109. #endif
  110. /* Realtime clock */
  111. #undef CONFIG_MCFRTC
  112. #define CONFIG_RTC_MCFRRTC
  113. #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
  114. /* Timer */
  115. #define CONFIG_MCFTMR
  116. /* I2c */
  117. #undef CONFIG_SYS_FSL_I2C
  118. #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  119. /* I2C speed and slave address */
  120. #define CONFIG_SYS_I2C_SPEED 80000
  121. #define CONFIG_SYS_I2C_SLAVE 0x7F
  122. #define CONFIG_SYS_I2C_OFFSET 0x58000
  123. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  124. /* DSPI and Serial Flash */
  125. #define CONFIG_CF_DSPI
  126. #define CONFIG_SERIAL_FLASH
  127. #define CONFIG_SYS_SBFHDR_SIZE 0x7
  128. /* Input, PCI, Flexbus, and VCO */
  129. #define CONFIG_EXTRA_CLOCK
  130. #define CONFIG_PRAM 2048 /* 2048 KB */
  131. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  132. #define CONFIG_SYS_MBAR 0xFC000000
  133. /*
  134. * Low Level Configuration Settings
  135. * (address mappings, register initial values, etc.)
  136. * You should know what you are doing if you make changes here.
  137. */
  138. /*-----------------------------------------------------------------------
  139. * Definitions for initial stack pointer and data area (in DPRAM)
  140. */
  141. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  142. /* End of used area in internal SRAM */
  143. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  144. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  145. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
  146. GENERATED_GBL_DATA_SIZE) - 32)
  147. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  148. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  149. /*-----------------------------------------------------------------------
  150. * Start addresses for the final memory configuration
  151. * (Set up by the startup code)
  152. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  153. */
  154. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  155. #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
  156. #define CONFIG_SYS_DRAM_TEST
  157. #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
  158. #define CONFIG_SERIAL_BOOT
  159. #endif
  160. #if defined(CONFIG_SERIAL_BOOT)
  161. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
  162. #else
  163. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  164. #endif
  165. #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
  166. /* Reserve 256 kB for Monitor */
  167. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  168. /* Reserve 256 kB for malloc() */
  169. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  170. /*
  171. * For booting Linux, the board info and command line data
  172. * have to be in the first 8 MB of memory, since this is
  173. * the maximum mapped by the Linux kernel during initialization ??
  174. */
  175. /* Initial Memory map for Linux */
  176. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
  177. (CONFIG_SYS_SDRAM_SIZE << 20))
  178. /* Configuration for environment
  179. * Environment is embedded in u-boot in the second sector of the flash
  180. */
  181. /* FLASH organization */
  182. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  183. #ifdef CONFIG_SYS_FLASH_CFI
  184. /* Max size that the board might have */
  185. #define CONFIG_SYS_FLASH_SIZE 0x1000000
  186. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  187. /* max number of memory banks */
  188. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  189. /* max number of sectors on one chip */
  190. #define CONFIG_SYS_MAX_FLASH_SECT 270
  191. /* "Real" (hardware) sectors protection */
  192. #define CONFIG_SYS_FLASH_CHECKSUM
  193. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
  194. #else
  195. /* max number of sectors on one chip */
  196. #define CONFIG_SYS_MAX_FLASH_SECT 270
  197. /* max number of sectors on one chip */
  198. #define CONFIG_SYS_MAX_FLASH_BANKS 0
  199. #endif
  200. /*
  201. * This is setting for JFFS2 support in u-boot.
  202. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  203. */
  204. #ifdef CONFIG_CMD_JFFS2
  205. #define CONFIG_JFFS2_DEV "nand0"
  206. #define CONFIG_JFFS2_PART_OFFSET (0x800000)
  207. #endif
  208. /* Cache Configuration */
  209. #define CONFIG_SYS_CACHELINE_SIZE 16
  210. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  211. CONFIG_SYS_INIT_RAM_SIZE - 8)
  212. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  213. CONFIG_SYS_INIT_RAM_SIZE - 4)
  214. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
  215. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  216. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  217. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  218. CF_ACR_EN | CF_ACR_SM_ALL)
  219. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
  220. CF_CACR_ICINVA | CF_CACR_EUSP)
  221. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  222. CF_CACR_DEC | CF_CACR_DDCM_P | \
  223. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  224. #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  225. CONFIG_SYS_INIT_RAM_SIZE - 12)
  226. /*-----------------------------------------------------------------------
  227. * Memory bank definitions
  228. */
  229. /*
  230. * CS0 - NOR Flash 16MB
  231. * CS1 - Available
  232. * CS2 - Available
  233. * CS3 - Available
  234. * CS4 - Available
  235. * CS5 - Available
  236. */
  237. /* Flash */
  238. #define CONFIG_SYS_CS0_BASE 0x00000000
  239. #define CONFIG_SYS_CS0_MASK 0x000F0101
  240. #define CONFIG_SYS_CS0_CTRL 0x00001D60
  241. #endif /* _M54418TWR_H */