M5282EVB.h 5.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Motorola MC5282EVB board.
  4. *
  5. * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef _CONFIG_M5282EVB_H
  11. #define _CONFIG_M5282EVB_H
  12. /*
  13. * High Level Configuration Options
  14. * (easy to change)
  15. */
  16. #define CONFIG_MCFTMR
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  20. /* Configuration for environment
  21. * Environment is embedded in u-boot in the second sector of the flash
  22. */
  23. #define LDS_BOARD_TEXT \
  24. . = DEFINED(env_offset) ? env_offset : .; \
  25. env/embedded.o(.text*);
  26. /*
  27. * BOOTP options
  28. */
  29. #define CONFIG_BOOTP_BOOTFILESIZE
  30. #ifdef CONFIG_MCFFEC
  31. # define CONFIG_MII_INIT 1
  32. # define CONFIG_SYS_DISCOVER_PHY
  33. # define CONFIG_SYS_RX_ETH_BUFFER 8
  34. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  35. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  36. # ifndef CONFIG_SYS_DISCOVER_PHY
  37. # define FECDUPLEX FULL
  38. # define FECSPEED _100BASET
  39. # else
  40. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  41. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  42. # endif
  43. # endif /* CONFIG_SYS_DISCOVER_PHY */
  44. #endif
  45. #ifdef CONFIG_MCFFEC
  46. # define CONFIG_IPADDR 192.162.1.2
  47. # define CONFIG_NETMASK 255.255.255.0
  48. # define CONFIG_SERVERIP 192.162.1.1
  49. # define CONFIG_GATEWAYIP 192.162.1.1
  50. #endif /* CONFIG_MCFFEC */
  51. #define CONFIG_HOSTNAME "M5282EVB"
  52. #define CONFIG_EXTRA_ENV_SETTINGS \
  53. "netdev=eth0\0" \
  54. "loadaddr=10000\0" \
  55. "u-boot=u-boot.bin\0" \
  56. "load=tftp ${loadaddr) ${u-boot}\0" \
  57. "upd=run load; run prog\0" \
  58. "prog=prot off ffe00000 ffe3ffff;" \
  59. "era ffe00000 ffe3ffff;" \
  60. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  61. "save\0" \
  62. ""
  63. #define CONFIG_SYS_LOAD_ADDR 0x20000
  64. #define CONFIG_SYS_CLK 64000000
  65. /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  66. #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
  67. #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
  68. /*
  69. * Low Level Configuration Settings
  70. * (address mappings, register initial values, etc.)
  71. * You should know what you are doing if you make changes here.
  72. */
  73. #define CONFIG_SYS_MBAR 0x40000000
  74. /*-----------------------------------------------------------------------
  75. * Definitions for initial stack pointer and data area (in DPRAM)
  76. */
  77. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  78. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  79. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  80. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  81. /*-----------------------------------------------------------------------
  82. * Start addresses for the final memory configuration
  83. * (Set up by the startup code)
  84. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  85. */
  86. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  87. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  88. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  89. #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
  90. #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
  91. /* If M5282 port is fully implemented the monitor base will be behind
  92. * the vector table. */
  93. #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
  94. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  95. #else
  96. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
  97. #endif
  98. #define CONFIG_SYS_MONITOR_LEN 0x20000
  99. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  100. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  101. /*
  102. * For booting Linux, the board info and command line data
  103. * have to be in the first 8 MB of memory, since this is
  104. * the maximum mapped by the Linux kernel during initialization ??
  105. */
  106. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  107. /*-----------------------------------------------------------------------
  108. * FLASH organization
  109. */
  110. #ifdef CONFIG_SYS_FLASH_CFI
  111. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  112. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  113. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  114. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  115. # define CONFIG_SYS_FLASH_CHECKSUM
  116. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  117. #endif
  118. /*-----------------------------------------------------------------------
  119. * Cache Configuration
  120. */
  121. #define CONFIG_SYS_CACHELINE_SIZE 16
  122. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  123. CONFIG_SYS_INIT_RAM_SIZE - 8)
  124. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  125. CONFIG_SYS_INIT_RAM_SIZE - 4)
  126. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
  127. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  128. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  129. CF_ACR_EN | CF_ACR_SM_ALL)
  130. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
  131. CF_CACR_CEIB | CF_CACR_DBWE | \
  132. CF_CACR_EUSP)
  133. /*-----------------------------------------------------------------------
  134. * Memory bank definitions
  135. */
  136. #define CONFIG_SYS_CS0_BASE 0xFFE00000
  137. #define CONFIG_SYS_CS0_CTRL 0x00001980
  138. #define CONFIG_SYS_CS0_MASK 0x001F0001
  139. /*-----------------------------------------------------------------------
  140. * Port configuration
  141. */
  142. #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
  143. #define CONFIG_SYS_PADDR 0x0000000
  144. #define CONFIG_SYS_PADAT 0x0000000
  145. #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
  146. #define CONFIG_SYS_PBDDR 0x0000000
  147. #define CONFIG_SYS_PBDAT 0x0000000
  148. #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
  149. #define CONFIG_SYS_PCDDR 0x0000000
  150. #define CONFIG_SYS_PCDAT 0x0000000
  151. #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
  152. #define CONFIG_SYS_PCDDR 0x0000000
  153. #define CONFIG_SYS_PCDAT 0x0000000
  154. #define CONFIG_SYS_PEHLPAR 0xC0
  155. #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
  156. #define CONFIG_SYS_DDRUA 0x05
  157. #define CONFIG_SYS_PJPAR 0xFF
  158. #endif /* _CONFIG_M5282EVB_H */