M5253DEMO.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3. * Hayden Fraser (Hayden.Fraser@freescale.com)
  4. */
  5. #ifndef _M5253DEMO_H
  6. #define _M5253DEMO_H
  7. #include <linux/stringify.h>
  8. #define CONFIG_MCFTMR
  9. #define CONFIG_MCFUART
  10. #define CONFIG_SYS_UART_PORT (0)
  11. #undef CONFIG_WATCHDOG /* disable watchdog */
  12. /* Configuration for environment
  13. * Environment is embedded in u-boot in the second sector of the flash
  14. */
  15. #define LDS_BOARD_TEXT \
  16. . = DEFINED(env_offset) ? env_offset : .; \
  17. env/embedded.o(.text*);
  18. #ifdef CONFIG_IDE
  19. /* ATA */
  20. # define CONFIG_IDE_RESET 1
  21. # define CONFIG_IDE_PREINIT 1
  22. # define CONFIG_ATAPI
  23. # undef CONFIG_LBA48
  24. # define CONFIG_SYS_IDE_MAXBUS 1
  25. # define CONFIG_SYS_IDE_MAXDEVICE 2
  26. # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  27. # define CONFIG_SYS_ATA_IDE0_OFFSET 0
  28. # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
  29. # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
  30. # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
  31. # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
  32. #endif
  33. #define CONFIG_DRIVER_DM9000
  34. #ifdef CONFIG_DRIVER_DM9000
  35. # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
  36. # define DM9000_IO CONFIG_DM9000_BASE
  37. # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  38. # undef CONFIG_DM9000_DEBUG
  39. # define CONFIG_DM9000_BYTE_SWAPPED
  40. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  41. # define CONFIG_EXTRA_ENV_SETTINGS \
  42. "netdev=eth0\0" \
  43. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  44. "loadaddr=10000\0" \
  45. "u-boot=u-boot.bin\0" \
  46. "load=tftp ${loadaddr) ${u-boot}\0" \
  47. "upd=run load; run prog\0" \
  48. "prog=prot off 0xff800000 0xff82ffff;" \
  49. "era 0xff800000 0xff82ffff;" \
  50. "cp.b ${loadaddr} 0xff800000 ${filesize};" \
  51. "save\0" \
  52. ""
  53. #endif
  54. #define CONFIG_HOSTNAME "M5253DEMO"
  55. /* I2C */
  56. #define CONFIG_SYS_I2C
  57. #define CONFIG_SYS_I2C_FSL
  58. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  59. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  60. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
  61. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  62. #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
  63. #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
  64. #define CONFIG_SYS_I2C_PINMUX_SET (0)
  65. #define CONFIG_SYS_LOAD_ADDR 0x00100000
  66. #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
  67. #define CONFIG_SYS_FAST_CLK
  68. #ifdef CONFIG_SYS_FAST_CLK
  69. # define CONFIG_SYS_PLLCR 0x1243E054
  70. # define CONFIG_SYS_CLK 140000000
  71. #else
  72. # define CONFIG_SYS_PLLCR 0x135a4140
  73. # define CONFIG_SYS_CLK 70000000
  74. #endif
  75. /*
  76. * Low Level Configuration Settings
  77. * (address mappings, register initial values, etc.)
  78. * You should know what you are doing if you make changes here.
  79. */
  80. #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
  81. #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
  82. /*
  83. * Definitions for initial stack pointer and data area (in DPRAM)
  84. */
  85. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  86. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  87. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  88. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  89. /*
  90. * Start addresses for the final memory configuration
  91. * (Set up by the startup code)
  92. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  93. */
  94. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  95. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  96. #ifdef CONFIG_MONITOR_IS_IN_RAM
  97. # define CONFIG_SYS_MONITOR_BASE 0x20000
  98. #else
  99. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  100. #endif
  101. #define CONFIG_SYS_MONITOR_LEN 0x40000
  102. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  103. #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
  104. /*
  105. * For booting Linux, the board info and command line data
  106. * have to be in the first 8 MB of memory, since this is
  107. * the maximum mapped by the Linux kernel during initialization ??
  108. */
  109. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  110. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  111. /* FLASH organization */
  112. #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  113. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  114. #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
  115. #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
  116. #define FLASH_SST6401B 0x200
  117. #define SST_ID_xF6401B 0x236D236D
  118. #ifdef CONFIG_SYS_FLASH_CFI
  119. /*
  120. * Unable to use CFI driver, due to incompatible sector erase command by SST.
  121. * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
  122. * 0x30 is block erase in SST
  123. */
  124. # define CONFIG_SYS_FLASH_SIZE 0x800000
  125. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  126. # define CONFIG_FLASH_CFI_LEGACY
  127. #else
  128. # define CONFIG_SYS_SST_SECT 2048
  129. # define CONFIG_SYS_SST_SECTSZ 0x1000
  130. # define CONFIG_SYS_FLASH_WRITE_TOUT 500
  131. #endif
  132. /* Cache Configuration */
  133. #define CONFIG_SYS_CACHELINE_SIZE 16
  134. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  135. CONFIG_SYS_INIT_RAM_SIZE - 8)
  136. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  137. CONFIG_SYS_INIT_RAM_SIZE - 4)
  138. #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
  139. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
  140. CF_ADDRMASK(8) | \
  141. CF_ACR_EN | CF_ACR_SM_ALL)
  142. #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
  143. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  144. CF_ACR_EN | CF_ACR_SM_ALL)
  145. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
  146. CF_CACR_DBWE)
  147. /* Port configuration */
  148. #define CONFIG_SYS_FECI2C 0xF0
  149. #define CONFIG_SYS_CS0_BASE 0xFF800000
  150. #define CONFIG_SYS_CS0_MASK 0x007F0021
  151. #define CONFIG_SYS_CS0_CTRL 0x00001D80
  152. #define CONFIG_SYS_CS1_BASE 0xE0000000
  153. #define CONFIG_SYS_CS1_MASK 0x00000001
  154. #define CONFIG_SYS_CS1_CTRL 0x00003DD8
  155. /*-----------------------------------------------------------------------
  156. * Port configuration
  157. */
  158. #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
  159. #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
  160. #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
  161. #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
  162. #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
  163. #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
  164. #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
  165. #endif /* _M5253DEMO_H */