M5235EVB.h 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5329 FireEngine board.
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5235EVB_H
  12. #define _M5235EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  21. /*
  22. * BOOTP options
  23. */
  24. #define CONFIG_BOOTP_BOOTFILESIZE
  25. #ifdef CONFIG_MCFFEC
  26. # define CONFIG_MII_INIT 1
  27. # define CONFIG_SYS_DISCOVER_PHY
  28. # define CONFIG_SYS_RX_ETH_BUFFER 8
  29. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  30. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  31. # ifndef CONFIG_SYS_DISCOVER_PHY
  32. # define FECDUPLEX FULL
  33. # define FECSPEED _100BASET
  34. # else
  35. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  36. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  37. # endif
  38. # endif /* CONFIG_SYS_DISCOVER_PHY */
  39. #endif
  40. /* Timer */
  41. #define CONFIG_MCFTMR
  42. /* I2C */
  43. #define CONFIG_SYS_I2C
  44. #define CONFIG_SYS_i2C_FSL
  45. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  46. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  47. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
  48. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  49. #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
  50. #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
  51. #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
  52. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  53. #define CONFIG_BOOTFILE "u-boot.bin"
  54. #ifdef CONFIG_MCFFEC
  55. # define CONFIG_IPADDR 192.162.1.2
  56. # define CONFIG_NETMASK 255.255.255.0
  57. # define CONFIG_SERVERIP 192.162.1.1
  58. # define CONFIG_GATEWAYIP 192.162.1.1
  59. #endif /* FEC_ENET */
  60. #define CONFIG_HOSTNAME "M5235EVB"
  61. #define CONFIG_EXTRA_ENV_SETTINGS \
  62. "netdev=eth0\0" \
  63. "loadaddr=10000\0" \
  64. "u-boot=u-boot.bin\0" \
  65. "load=tftp ${loadaddr) ${u-boot}\0" \
  66. "upd=run load; run prog\0" \
  67. "prog=prot off ffe00000 ffe3ffff;" \
  68. "era ffe00000 ffe3ffff;" \
  69. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  70. "save\0" \
  71. ""
  72. #define CONFIG_PRAM 512 /* 512 KB */
  73. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
  74. #define CONFIG_SYS_CLK 75000000
  75. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
  76. #define CONFIG_SYS_MBAR 0x40000000
  77. /*
  78. * Low Level Configuration Settings
  79. * (address mappings, register initial values, etc.)
  80. * You should know what you are doing if you make changes here.
  81. */
  82. /*-----------------------------------------------------------------------
  83. * Definitions for initial stack pointer and data area (in DPRAM)
  84. */
  85. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  86. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  87. #define CONFIG_SYS_INIT_RAM_CTRL 0x21
  88. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
  89. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  90. /*-----------------------------------------------------------------------
  91. * Start addresses for the final memory configuration
  92. * (Set up by the startup code)
  93. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  94. */
  95. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  96. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  97. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  98. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  99. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  100. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  101. /*
  102. * For booting Linux, the board info and command line data
  103. * have to be in the first 8 MB of memory, since this is
  104. * the maximum mapped by the Linux kernel during initialization ??
  105. */
  106. /* Initial Memory map for Linux */
  107. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  108. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  109. /*-----------------------------------------------------------------------
  110. * FLASH organization
  111. */
  112. #ifdef CONFIG_SYS_FLASH_CFI
  113. # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
  114. #ifdef NORFLASH_PS32BIT
  115. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  116. #else
  117. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  118. #endif
  119. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  120. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  121. #endif
  122. #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  123. /* Configuration for environment
  124. * Environment is embedded in u-boot in the second sector of the flash
  125. */
  126. #define LDS_BOARD_TEXT \
  127. . = DEFINED(env_offset) ? env_offset : .; \
  128. env/embedded.o(.text);
  129. /*-----------------------------------------------------------------------
  130. * Cache Configuration
  131. */
  132. #define CONFIG_SYS_CACHELINE_SIZE 16
  133. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  134. CONFIG_SYS_INIT_RAM_SIZE - 8)
  135. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  136. CONFIG_SYS_INIT_RAM_SIZE - 4)
  137. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
  138. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  139. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  140. CF_ACR_EN | CF_ACR_SM_ALL)
  141. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
  142. CF_CACR_CEIB | CF_CACR_DCM | \
  143. CF_CACR_EUSP)
  144. /*-----------------------------------------------------------------------
  145. * Chipselect bank definitions
  146. */
  147. /*
  148. * CS0 - NOR Flash 1, 2, 4, or 8MB
  149. * CS1 - Available
  150. * CS2 - Available
  151. * CS3 - Available
  152. * CS4 - Available
  153. * CS5 - Available
  154. * CS6 - Available
  155. * CS7 - Available
  156. */
  157. #ifdef NORFLASH_PS32BIT
  158. # define CONFIG_SYS_CS0_BASE 0xFFC00000
  159. # define CONFIG_SYS_CS0_MASK 0x003f0001
  160. # define CONFIG_SYS_CS0_CTRL 0x00001D00
  161. #else
  162. # define CONFIG_SYS_CS0_BASE 0xFFE00000
  163. # define CONFIG_SYS_CS0_MASK 0x001f0001
  164. # define CONFIG_SYS_CS0_CTRL 0x00001D80
  165. #endif
  166. #endif /* _M5329EVB_H */