M5208EVBE.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5208EVBe.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. #ifndef _M5208EVBE_H
  9. #define _M5208EVBE_H
  10. /*
  11. * High Level Configuration Options
  12. * (easy to change)
  13. */
  14. #define CONFIG_MCFUART
  15. #define CONFIG_SYS_UART_PORT (0)
  16. #undef CONFIG_WATCHDOG
  17. #define CONFIG_WATCHDOG_TIMEOUT 5000
  18. #ifdef CONFIG_MCFFEC
  19. # define CONFIG_MII_INIT 1
  20. # define CONFIG_SYS_DISCOVER_PHY
  21. # define CONFIG_SYS_RX_ETH_BUFFER 8
  22. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  23. # define CONFIG_HAS_ETH1
  24. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  25. # ifndef CONFIG_SYS_DISCOVER_PHY
  26. # define FECDUPLEX FULL
  27. # define FECSPEED _100BASET
  28. # else
  29. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  30. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  31. # endif
  32. # endif /* CONFIG_SYS_DISCOVER_PHY */
  33. #endif
  34. /* Timer */
  35. #define CONFIG_MCFTMR
  36. /* I2C */
  37. #define CONFIG_SYS_I2C
  38. #define CONFIG_SYS_I2C_FSL
  39. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  40. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  41. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  42. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  43. #define CONFIG_UDP_CHECKSUM
  44. #ifdef CONFIG_MCFFEC
  45. # define CONFIG_IPADDR 192.162.1.2
  46. # define CONFIG_NETMASK 255.255.255.0
  47. # define CONFIG_SERVERIP 192.162.1.1
  48. # define CONFIG_GATEWAYIP 192.162.1.1
  49. #endif /* CONFIG_MCFFEC */
  50. #define CONFIG_HOSTNAME "M5208EVBe"
  51. #define CONFIG_EXTRA_ENV_SETTINGS \
  52. "netdev=eth0\0" \
  53. "loadaddr=40010000\0" \
  54. "u-boot=u-boot.bin\0" \
  55. "load=tftp ${loadaddr) ${u-boot}\0" \
  56. "upd=run load; run prog\0" \
  57. "prog=prot off 0 3ffff;" \
  58. "era 0 3ffff;" \
  59. "cp.b ${loadaddr} 0 ${filesize};" \
  60. "save\0" \
  61. ""
  62. #define CONFIG_PRAM 512 /* 512 KB */
  63. #define CONFIG_SYS_LOAD_ADDR 0x40010000
  64. #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
  65. #define CONFIG_SYS_PLL_ODR 0x36
  66. #define CONFIG_SYS_PLL_FDR 0x7D
  67. #define CONFIG_SYS_MBAR 0xFC000000
  68. /*
  69. * Low Level Configuration Settings
  70. * (address mappings, register initial values, etc.)
  71. * You should know what you are doing if you make changes here.
  72. */
  73. /* Definitions for initial stack pointer and data area (in DPRAM) */
  74. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  75. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
  76. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  77. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  78. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  79. /*
  80. * Start addresses for the final memory configuration
  81. * (Set up by the startup code)
  82. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  83. */
  84. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  85. #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
  86. #define CONFIG_SYS_SDRAM_CFG1 0x43711630
  87. #define CONFIG_SYS_SDRAM_CFG2 0x56670000
  88. #define CONFIG_SYS_SDRAM_CTRL 0xE1002000
  89. #define CONFIG_SYS_SDRAM_EMOD 0x80010000
  90. #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
  91. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  92. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  93. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  94. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  95. /*
  96. * For booting Linux, the board info and command line data
  97. * have to be in the first 8 MB of memory, since this is
  98. * the maximum mapped by the Linux kernel during initialization ??
  99. */
  100. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  101. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  102. /* FLASH organization */
  103. #ifdef CONFIG_SYS_FLASH_CFI
  104. # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
  105. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  106. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  107. # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
  108. #endif
  109. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  110. /*
  111. * Configuration for environment
  112. * Environment is embedded in u-boot in the second sector of the flash
  113. */
  114. #define LDS_BOARD_TEXT \
  115. . = DEFINED(env_offset) ? env_offset : .; \
  116. env/embedded.o(.text*);
  117. /* Cache Configuration */
  118. #define CONFIG_SYS_CACHELINE_SIZE 16
  119. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  120. CONFIG_SYS_INIT_RAM_SIZE - 8)
  121. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  122. CONFIG_SYS_INIT_RAM_SIZE - 4)
  123. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
  124. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  125. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  126. CF_ACR_EN | CF_ACR_SM_ALL)
  127. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
  128. CF_CACR_DISD | CF_CACR_INVI | \
  129. CF_CACR_CEIB | CF_CACR_DCM | \
  130. CF_CACR_EUSP)
  131. /* Chipselect bank definitions */
  132. /*
  133. * CS0 - NOR Flash
  134. * CS1 - Available
  135. * CS2 - Available
  136. * CS3 - Available
  137. * CS4 - Available
  138. * CS5 - Available
  139. */
  140. #define CONFIG_SYS_CS0_BASE 0
  141. #define CONFIG_SYS_CS0_MASK 0x007F0001
  142. #define CONFIG_SYS_CS0_CTRL 0x00001FA0
  143. #endif /* _M5208EVBE_H */