common_timing_params.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef COMMON_TIMING_PARAMS_H
  6. #define COMMON_TIMING_PARAMS_H
  7. typedef struct {
  8. /* parameters to constrict */
  9. unsigned int tckmin_x_ps;
  10. unsigned int tckmax_ps;
  11. unsigned int trcd_ps;
  12. unsigned int trp_ps;
  13. unsigned int tras_ps;
  14. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  15. unsigned int taamin_ps;
  16. #endif
  17. #ifdef CONFIG_SYS_FSL_DDR4
  18. unsigned int trfc1_ps;
  19. unsigned int trfc2_ps;
  20. unsigned int trfc4_ps;
  21. unsigned int trrds_ps;
  22. unsigned int trrdl_ps;
  23. unsigned int tccdl_ps;
  24. unsigned int trfc_slr_ps;
  25. #else
  26. unsigned int twtr_ps; /* maximum = 63750 ps */
  27. unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns
  28. = 511750 ps */
  29. unsigned int trrd_ps; /* maximum = 63750 ps */
  30. unsigned int trtp_ps; /* byte 38, spd->trtp */
  31. #endif
  32. unsigned int twr_ps; /* maximum = 63750 ps */
  33. unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
  34. unsigned int refresh_rate_ps;
  35. unsigned int extended_op_srt;
  36. #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
  37. unsigned int tis_ps; /* byte 32, spd->ca_setup */
  38. unsigned int tih_ps; /* byte 33, spd->ca_hold */
  39. unsigned int tds_ps; /* byte 34, spd->data_setup */
  40. unsigned int tdh_ps; /* byte 35, spd->data_hold */
  41. unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
  42. unsigned int tqhs_ps; /* byte 45, spd->tqhs */
  43. #endif
  44. unsigned int ndimms_present;
  45. unsigned int lowest_common_spd_caslat;
  46. unsigned int highest_common_derated_caslat;
  47. unsigned int additive_latency;
  48. unsigned int all_dimms_burst_lengths_bitmask;
  49. unsigned int all_dimms_registered;
  50. unsigned int all_dimms_unbuffered;
  51. unsigned int all_dimms_ecc_capable;
  52. unsigned long long total_mem;
  53. unsigned long long base_address;
  54. /* DDR3 RDIMM */
  55. unsigned char rcw[16]; /* Register Control Word 0-15 */
  56. } common_timing_params_t;
  57. #endif