atmel_hlcdc.h 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Header file for AT91/AT32 MULTI LAYER LCD Controller
  4. *
  5. * Data structure and register user interface
  6. *
  7. * Copyright (C) 2012 Atmel Corporation
  8. */
  9. #ifndef __ATMEL_HLCDC_H__
  10. #define __ATMEL_HLCDC_H__
  11. /* Atmel multi layer lcdc hardware registers */
  12. struct atmel_hlcd_regs {
  13. u32 lcdc_lcdcfg0;
  14. u32 lcdc_lcdcfg1;
  15. u32 lcdc_lcdcfg2;
  16. u32 lcdc_lcdcfg3;
  17. u32 lcdc_lcdcfg4;
  18. u32 lcdc_lcdcfg5;
  19. u32 lcdc_lcdcfg6;
  20. u32 res1;
  21. u32 lcdc_lcden;
  22. u32 lcdc_lcddis;
  23. u32 lcdc_lcdsr;
  24. u32 res2;
  25. u32 lcdc_lcdidr;
  26. u32 res3[3];
  27. u32 lcdc_basecher;
  28. u32 res4[3];
  29. u32 lcdc_baseidr;
  30. u32 res5[3];
  31. u32 lcdc_baseaddr;
  32. u32 lcdc_basectrl;
  33. u32 lcdc_basenext;
  34. u32 lcdc_basecfg0;
  35. u32 lcdc_basecfg1;
  36. u32 lcdc_basecfg2;
  37. u32 lcdc_basecfg3;
  38. u32 lcdc_basecfg4;
  39. };
  40. #define LCDC_LCDCFG0_CLKPOL (0x1 << 0)
  41. #define LCDC_LCDCFG0_CLKSEL (0x1 << 2)
  42. #define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3)
  43. #define LCDC_LCDCFG0_CGDISBASE (0x1 << 8)
  44. #define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9)
  45. #define LCDC_LCDCFG0_CGDISHEO (0x1 << 11)
  46. #define LCDC_LCDCFG0_CGDISHCR (0x1 << 12)
  47. #define LCDC_LCDCFG0_CLKDIV_Pos 16
  48. #define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos)
  49. #define LCDC_LCDCFG0_CLKDIV(value) \
  50. ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
  51. #define LCDC_LCDCFG1_HSPW_Pos 0
  52. #define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos)
  53. #define LCDC_LCDCFG1_HSPW(value) \
  54. ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
  55. #define LCDC_LCDCFG1_VSPW_Pos 16
  56. #define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos)
  57. #define LCDC_LCDCFG1_VSPW(value) \
  58. ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
  59. #define LCDC_LCDCFG2_VFPW_Pos 0
  60. #define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos)
  61. #define LCDC_LCDCFG2_VFPW(value) \
  62. ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
  63. #define LCDC_LCDCFG2_VBPW_Pos 16
  64. #define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos)
  65. #define LCDC_LCDCFG2_VBPW(value) \
  66. ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
  67. #define LCDC_LCDCFG3_HFPW_Pos 0
  68. #define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos)
  69. #define LCDC_LCDCFG3_HFPW(value) \
  70. ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
  71. #define LCDC_LCDCFG3_HBPW_Pos 16
  72. #define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos)
  73. #define LCDC_LCDCFG3_HBPW(value) \
  74. ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
  75. #define LCDC_LCDCFG4_PPL_Pos 0
  76. #define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos)
  77. #define LCDC_LCDCFG4_PPL(value) \
  78. ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
  79. #define LCDC_LCDCFG4_RPF_Pos 16
  80. #define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos)
  81. #define LCDC_LCDCFG4_RPF(value) \
  82. ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
  83. #define LCDC_LCDCFG5_HSPOL (0x1 << 0)
  84. #define LCDC_LCDCFG5_VSPOL (0x1 << 1)
  85. #define LCDC_LCDCFG5_VSPDLYS (0x1 << 2)
  86. #define LCDC_LCDCFG5_VSPDLYE (0x1 << 3)
  87. #define LCDC_LCDCFG5_DISPPOL (0x1 << 4)
  88. #define LCDC_LCDCFG5_SERIAL (0x1 << 5)
  89. #define LCDC_LCDCFG5_DITHER (0x1 << 6)
  90. #define LCDC_LCDCFG5_DISPDLY (0x1 << 7)
  91. #define LCDC_LCDCFG5_MODE_Pos 8
  92. #define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos)
  93. #define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8)
  94. #define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8)
  95. #define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8)
  96. #define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8)
  97. #define LCDC_LCDCFG5_VSPSU (0x1 << 12)
  98. #define LCDC_LCDCFG5_VSPHO (0x1 << 13)
  99. #define LCDC_LCDCFG5_GUARDTIME_Pos 16
  100. #define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
  101. #define LCDC_LCDCFG5_GUARDTIME(value) \
  102. ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
  103. #define LCDC_LCDCFG6_PWMPS_Pos 0
  104. #define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos)
  105. #define LCDC_LCDCFG6_PWMPS(value) \
  106. ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
  107. #define LCDC_LCDCFG6_PWMPOL (0x1 << 4)
  108. #define LCDC_LCDCFG6_PWMCVAL_Pos 8
  109. #define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
  110. #define LCDC_LCDCFG6_PWMCVAL(value) \
  111. ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
  112. #define LCDC_LCDEN_CLKEN (0x1 << 0)
  113. #define LCDC_LCDEN_SYNCEN (0x1 << 1)
  114. #define LCDC_LCDEN_DISPEN (0x1 << 2)
  115. #define LCDC_LCDEN_PWMEN (0x1 << 3)
  116. #define LCDC_LCDDIS_CLKDIS (0x1 << 0)
  117. #define LCDC_LCDDIS_SYNCDIS (0x1 << 1)
  118. #define LCDC_LCDDIS_DISPDIS (0x1 << 2)
  119. #define LCDC_LCDDIS_PWMDIS (0x1 << 3)
  120. #define LCDC_LCDDIS_CLKRST (0x1 << 8)
  121. #define LCDC_LCDDIS_SYNCRST (0x1 << 9)
  122. #define LCDC_LCDDIS_DISPRST (0x1 << 10)
  123. #define LCDC_LCDDIS_PWMRST (0x1 << 11)
  124. #define LCDC_LCDSR_CLKSTS (0x1 << 0)
  125. #define LCDC_LCDSR_LCDSTS (0x1 << 1)
  126. #define LCDC_LCDSR_DISPSTS (0x1 << 2)
  127. #define LCDC_LCDSR_PWMSTS (0x1 << 3)
  128. #define LCDC_LCDSR_SIPSTS (0x1 << 4)
  129. #define LCDC_LCDIDR_SOFID (0x1 << 0)
  130. #define LCDC_LCDIDR_DISID (0x1 << 1)
  131. #define LCDC_LCDIDR_DISPID (0x1 << 2)
  132. #define LCDC_LCDIDR_FIFOERRID (0x1 << 4)
  133. #define LCDC_LCDIDR_BASEID (0x1 << 8)
  134. #define LCDC_LCDIDR_OVR1ID (0x1 << 9)
  135. #define LCDC_LCDIDR_HEOID (0x1 << 11)
  136. #define LCDC_LCDIDR_HCRID (0x1 << 12)
  137. #define LCDC_BASECHER_CHEN (0x1 << 0)
  138. #define LCDC_BASECHER_UPDATEEN (0x1 << 1)
  139. #define LCDC_BASECHER_A2QEN (0x1 << 2)
  140. #define LCDC_BASEIDR_DMA (0x1 << 2)
  141. #define LCDC_BASEIDR_DSCR (0x1 << 3)
  142. #define LCDC_BASEIDR_ADD (0x1 << 4)
  143. #define LCDC_BASEIDR_DONE (0x1 << 5)
  144. #define LCDC_BASEIDR_OVR (0x1 << 6)
  145. #define LCDC_BASECTRL_DFETCH (0x1 << 0)
  146. #define LCDC_BASECTRL_LFETCH (0x1 << 1)
  147. #define LCDC_BASECTRL_DMAIEN (0x1 << 2)
  148. #define LCDC_BASECTRL_DSCRIEN (0x1 << 3)
  149. #define LCDC_BASECTRL_ADDIEN (0x1 << 4)
  150. #define LCDC_BASECTRL_DONEIEN (0x1 << 5)
  151. #define LCDC_BASECFG0_BLEN_Pos 4
  152. #define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4)
  153. #define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4)
  154. #define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4)
  155. #define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4)
  156. #define LCDC_BASECFG0_DLBO (0x1 << 8)
  157. #define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4)
  158. #define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4)
  159. #define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4)
  160. #define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4)
  161. #define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4)
  162. #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4)
  163. #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4)
  164. #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4)
  165. #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4)
  166. #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4)
  167. #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4)
  168. #define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4)
  169. #define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4)
  170. #define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4)
  171. #define LCDC_BASECFG2_XSTRIDE_Pos 0
  172. #define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
  173. #define LCDC_BASECFG2_XSTRIDE(value) \
  174. ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
  175. #define LCDC_BASECFG3_BDEF_Pos 0
  176. #define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos)
  177. #define LCDC_BASECFG3_BDEF(value) \
  178. ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
  179. #define LCDC_BASECFG3_GDEF_Pos 8
  180. #define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos)
  181. #define LCDC_BASECFG3_GDEF(value) \
  182. ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
  183. #define LCDC_BASECFG3_RDEF_Pos 16
  184. #define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos)
  185. #define LCDC_BASECFG3_RDEF(value) \
  186. ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
  187. #define LCDC_BASECLUT_BCLUT_Pos 0
  188. #define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos)
  189. #define LCDC_BASECLUT_GCLUT_Pos 8
  190. #define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos)
  191. #define LCDC_BASECLUT_RCLUT_Pos 16
  192. #define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos)
  193. #define LCDC_BASECFG4_DMA (0x1 << 8)
  194. #define LCDC_BASECFG4_REP (0x1 << 9)
  195. struct lcd_dma_desc {
  196. u32 address;
  197. u32 control;
  198. u32 next;
  199. };
  200. #define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4))
  201. #endif /* __ATMEL_HLCDC_H__ */