mt7621_wdt.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Ralink / Mediatek RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
  4. *
  5. * Copyright (C) 2018 Stefan Roese <sr@denx.de>
  6. *
  7. * Based on the Linux driver version which is:
  8. * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  9. * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <wdt.h>
  14. #include <linux/bitops.h>
  15. #include <linux/io.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. struct mt762x_wdt {
  18. void __iomem *regs;
  19. };
  20. #define TIMER_REG_TMRSTAT 0x00
  21. #define TIMER_REG_TMR1CTL 0x20
  22. #define TIMER_REG_TMR1LOAD 0x24
  23. #define TMR1CTL_ENABLE BIT(7)
  24. #define TMR1CTL_RESTART BIT(9)
  25. #define TMR1CTL_PRESCALE_SHIFT 16
  26. static int mt762x_wdt_ping(struct mt762x_wdt *priv)
  27. {
  28. writel(TMR1CTL_RESTART, priv->regs + TIMER_REG_TMRSTAT);
  29. return 0;
  30. }
  31. static int mt762x_wdt_start(struct udevice *dev, u64 ms, ulong flags)
  32. {
  33. struct mt762x_wdt *priv = dev_get_priv(dev);
  34. /* set the prescaler to 1ms == 1000us */
  35. writel(1000 << TMR1CTL_PRESCALE_SHIFT, priv->regs + TIMER_REG_TMR1CTL);
  36. writel(ms, priv->regs + TIMER_REG_TMR1LOAD);
  37. setbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
  38. return 0;
  39. }
  40. static int mt762x_wdt_stop(struct udevice *dev)
  41. {
  42. struct mt762x_wdt *priv = dev_get_priv(dev);
  43. mt762x_wdt_ping(priv);
  44. clrbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
  45. return 0;
  46. }
  47. static int mt762x_wdt_reset(struct udevice *dev)
  48. {
  49. struct mt762x_wdt *priv = dev_get_priv(dev);
  50. mt762x_wdt_ping(priv);
  51. return 0;
  52. }
  53. static int mt762x_wdt_probe(struct udevice *dev)
  54. {
  55. struct mt762x_wdt *priv = dev_get_priv(dev);
  56. priv->regs = dev_remap_addr(dev);
  57. if (!priv->regs)
  58. return -EINVAL;
  59. mt762x_wdt_stop(dev);
  60. return 0;
  61. }
  62. static const struct wdt_ops mt762x_wdt_ops = {
  63. .start = mt762x_wdt_start,
  64. .reset = mt762x_wdt_reset,
  65. .stop = mt762x_wdt_stop,
  66. };
  67. static const struct udevice_id mt762x_wdt_ids[] = {
  68. { .compatible = "mediatek,mt7621-wdt" },
  69. {}
  70. };
  71. U_BOOT_DRIVER(mt762x_wdt) = {
  72. .name = "mt762x_wdt",
  73. .id = UCLASS_WDT,
  74. .of_match = mt762x_wdt_ids,
  75. .probe = mt762x_wdt_probe,
  76. .priv_auto_alloc_size = sizeof(struct mt762x_wdt),
  77. .ops = &mt762x_wdt_ops,
  78. };