ast_wdt.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include <wdt.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/wdt.h>
  12. #include <linux/err.h>
  13. #define WDT_AST2500 2500
  14. #define WDT_AST2400 2400
  15. struct ast_wdt_priv {
  16. struct ast_wdt *regs;
  17. };
  18. static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  19. {
  20. struct ast_wdt_priv *priv = dev_get_priv(dev);
  21. ulong driver_data = dev_get_driver_data(dev);
  22. u32 reset_mode = ast_reset_mode_from_flags(flags);
  23. /* 32 bits at 1MHz is 4294967ms */
  24. timeout = min_t(u64, timeout, 4294967);
  25. /* WDT counts in ticks of 1MHz clock. 1ms / 1e3 * 1e6 */
  26. timeout *= 1000;
  27. clrsetbits_le32(&priv->regs->ctrl,
  28. WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT,
  29. reset_mode << WDT_CTRL_RESET_MODE_SHIFT);
  30. if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC)
  31. writel(ast_reset_mask_from_flags(flags),
  32. &priv->regs->reset_mask);
  33. writel((u32) timeout, &priv->regs->counter_reload_val);
  34. writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
  35. /*
  36. * Setting CLK1MHZ bit is just for compatibility with ast2400 part.
  37. * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
  38. * read-only
  39. */
  40. setbits_le32(&priv->regs->ctrl,
  41. WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
  42. return 0;
  43. }
  44. static int ast_wdt_stop(struct udevice *dev)
  45. {
  46. struct ast_wdt_priv *priv = dev_get_priv(dev);
  47. clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);
  48. writel(WDT_RESET_DEFAULT, &priv->regs->reset_mask);
  49. return 0;
  50. }
  51. static int ast_wdt_reset(struct udevice *dev)
  52. {
  53. struct ast_wdt_priv *priv = dev_get_priv(dev);
  54. writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
  55. return 0;
  56. }
  57. static int ast_wdt_expire_now(struct udevice *dev, ulong flags)
  58. {
  59. struct ast_wdt_priv *priv = dev_get_priv(dev);
  60. int ret;
  61. ret = ast_wdt_start(dev, 1, flags);
  62. if (ret)
  63. return ret;
  64. while (readl(&priv->regs->ctrl) & WDT_CTRL_EN)
  65. ;
  66. return ast_wdt_stop(dev);
  67. }
  68. static int ast_wdt_ofdata_to_platdata(struct udevice *dev)
  69. {
  70. struct ast_wdt_priv *priv = dev_get_priv(dev);
  71. priv->regs = dev_read_addr_ptr(dev);
  72. if (!priv->regs)
  73. return -EINVAL;
  74. return 0;
  75. }
  76. static const struct wdt_ops ast_wdt_ops = {
  77. .start = ast_wdt_start,
  78. .reset = ast_wdt_reset,
  79. .stop = ast_wdt_stop,
  80. .expire_now = ast_wdt_expire_now,
  81. };
  82. static const struct udevice_id ast_wdt_ids[] = {
  83. { .compatible = "aspeed,wdt", .data = WDT_AST2500 },
  84. { .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 },
  85. { .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 },
  86. {}
  87. };
  88. static int ast_wdt_probe(struct udevice *dev)
  89. {
  90. debug("%s() wdt%u\n", __func__, dev->seq);
  91. ast_wdt_stop(dev);
  92. return 0;
  93. }
  94. U_BOOT_DRIVER(ast_wdt) = {
  95. .name = "ast_wdt",
  96. .id = UCLASS_WDT,
  97. .of_match = ast_wdt_ids,
  98. .probe = ast_wdt_probe,
  99. .priv_auto_alloc_size = sizeof(struct ast_wdt_priv),
  100. .ofdata_to_platdata = ast_wdt_ofdata_to_platdata,
  101. .ops = &ast_wdt_ops,
  102. };