armada-37xx-wdt.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell Armada 37xx SoC Watchdog Driver
  4. *
  5. * Marek Behun <marek.behun@nic.cz>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <wdt.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/soc.h>
  13. #include <dm/device_compat.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. struct a37xx_wdt {
  16. void __iomem *sel_reg;
  17. void __iomem *reg;
  18. ulong clk_rate;
  19. u64 timeout;
  20. };
  21. /*
  22. * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
  23. */
  24. #define CNTR_CTRL(id) ((id) * 0x10)
  25. #define CNTR_CTRL_ENABLE 0x0001
  26. #define CNTR_CTRL_ACTIVE 0x0002
  27. #define CNTR_CTRL_MODE_MASK 0x000c
  28. #define CNTR_CTRL_MODE_ONESHOT 0x0000
  29. #define CNTR_CTRL_MODE_HWSIG 0x000c
  30. #define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
  31. #define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
  32. #define CNTR_CTRL_PRESCALE_MASK 0xff00
  33. #define CNTR_CTRL_PRESCALE_MIN 2
  34. #define CNTR_CTRL_PRESCALE_SHIFT 8
  35. #define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
  36. #define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
  37. static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val)
  38. {
  39. writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id));
  40. writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id));
  41. }
  42. static void counter_enable(struct a37xx_wdt *priv, int id)
  43. {
  44. setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
  45. }
  46. static void counter_disable(struct a37xx_wdt *priv, int id)
  47. {
  48. clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
  49. }
  50. static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
  51. {
  52. u32 reg;
  53. reg = readl(priv->reg + CNTR_CTRL(id));
  54. if (reg & CNTR_CTRL_ACTIVE)
  55. return -EBUSY;
  56. reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
  57. CNTR_CTRL_TRIG_SRC_MASK);
  58. /* set mode */
  59. reg |= mode;
  60. /* set prescaler to the min value */
  61. reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
  62. /* set trigger source */
  63. reg |= trig_src;
  64. writel(reg, priv->reg + CNTR_CTRL(id));
  65. return 0;
  66. }
  67. static int a37xx_wdt_reset(struct udevice *dev)
  68. {
  69. struct a37xx_wdt *priv = dev_get_priv(dev);
  70. if (!priv->timeout)
  71. return -EINVAL;
  72. /* counter 1 is retriggered by forcing end count on counter 0 */
  73. counter_disable(priv, 0);
  74. counter_enable(priv, 0);
  75. return 0;
  76. }
  77. static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)
  78. {
  79. struct a37xx_wdt *priv = dev_get_priv(dev);
  80. /* first we set timeout to 0 */
  81. counter_disable(priv, 1);
  82. set_counter_value(priv, 1, 0);
  83. counter_enable(priv, 1);
  84. /* and then we start counter 1 by forcing end count on counter 0 */
  85. counter_disable(priv, 0);
  86. counter_enable(priv, 0);
  87. return 0;
  88. }
  89. static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
  90. {
  91. struct a37xx_wdt *priv = dev_get_priv(dev);
  92. int err;
  93. err = init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
  94. if (err < 0)
  95. return err;
  96. err = init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG,
  97. CNTR_CTRL_TRIG_SRC_PREV_CNTR);
  98. if (err < 0)
  99. return err;
  100. priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
  101. set_counter_value(priv, 0, 0);
  102. set_counter_value(priv, 1, priv->timeout);
  103. counter_enable(priv, 1);
  104. /* we have to force end count on counter 0 to start counter 1 */
  105. counter_enable(priv, 0);
  106. return 0;
  107. }
  108. static int a37xx_wdt_stop(struct udevice *dev)
  109. {
  110. struct a37xx_wdt *priv = dev_get_priv(dev);
  111. counter_disable(priv, 1);
  112. counter_disable(priv, 0);
  113. writel(0, priv->sel_reg);
  114. return 0;
  115. }
  116. static int a37xx_wdt_probe(struct udevice *dev)
  117. {
  118. struct a37xx_wdt *priv = dev_get_priv(dev);
  119. fdt_addr_t addr;
  120. addr = dev_read_addr_index(dev, 0);
  121. if (addr == FDT_ADDR_T_NONE)
  122. goto err;
  123. priv->sel_reg = (void __iomem *)addr;
  124. addr = dev_read_addr_index(dev, 1);
  125. if (addr == FDT_ADDR_T_NONE)
  126. goto err;
  127. priv->reg = (void __iomem *)addr;
  128. priv->clk_rate = (ulong)get_ref_clk() * 1000000;
  129. /*
  130. * We use counter 1 as watchdog timer, therefore we only set bit
  131. * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on
  132. * counter 1.
  133. */
  134. writel(1 << 1, priv->sel_reg);
  135. return 0;
  136. err:
  137. dev_err(dev, "no io address\n");
  138. return -ENODEV;
  139. }
  140. static const struct wdt_ops a37xx_wdt_ops = {
  141. .start = a37xx_wdt_start,
  142. .reset = a37xx_wdt_reset,
  143. .stop = a37xx_wdt_stop,
  144. .expire_now = a37xx_wdt_expire_now,
  145. };
  146. static const struct udevice_id a37xx_wdt_ids[] = {
  147. { .compatible = "marvell,armada-3700-wdt" },
  148. {}
  149. };
  150. U_BOOT_DRIVER(a37xx_wdt) = {
  151. .name = "armada_37xx_wdt",
  152. .id = UCLASS_WDT,
  153. .of_match = a37xx_wdt_ids,
  154. .probe = a37xx_wdt_probe,
  155. .priv_auto_alloc_size = sizeof(struct a37xx_wdt),
  156. .ops = &a37xx_wdt_ops,
  157. };