mxc_w1.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for one wire controller in some i.MX Socs
  4. *
  5. * There are currently two silicon variants:
  6. * V1: i.MX21, i.MX27, i.MX31, i.MX51
  7. * V2: i.MX25, i.MX35, i.MX50, i.MX53
  8. * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
  9. *
  10. * The V1 controller only supports single bit operations.
  11. * The V2 controller is backwards compatible on the register level but adds
  12. * byte size operations and a "search ROM accelerator mode"
  13. *
  14. * This driver does not currently support the search ROM accelerator
  15. *
  16. * Copyright (c) 2018 Flowbird
  17. * Martin Fuzzey <martin.fuzzey@flowbird.group>
  18. */
  19. #include <asm/arch/clock.h>
  20. #include <common.h>
  21. #include <dm.h>
  22. #include <dm/device_compat.h>
  23. #include <linux/bitops.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <w1.h>
  27. struct mxc_w1_regs {
  28. u16 control;
  29. #define MXC_W1_CONTROL_RPP BIT(7)
  30. #define MXC_W1_CONTROL_PST BIT(6)
  31. #define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
  32. #define MXC_W1_CONTROL_RDST BIT(3)
  33. u16 time_divider;
  34. u16 reset;
  35. /* Registers below on V2 silicon only */
  36. u16 command;
  37. u16 tx_rx;
  38. u16 interrupt;
  39. #define MXC_W1_INTERRUPT_TBE BIT(2)
  40. #define MXC_W1_INTERRUPT_TSRE BIT(3)
  41. #define MXC_W1_INTERRUPT_RBF BIT(4)
  42. #define MXC_W1_INTERRUPT_RSRF BIT(5)
  43. u16 interrupt_en;
  44. };
  45. struct mxc_w1_pdata {
  46. struct mxc_w1_regs *regs;
  47. };
  48. /*
  49. * this is the low level routine to read/write a bit on the One Wire
  50. * interface on the hardware. It does write 0 if parameter bit is set
  51. * to 0, otherwise a write 1/read.
  52. */
  53. static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
  54. {
  55. u16 *ctrl_addr = &pdata->regs->control;
  56. u16 mask = MXC_W1_CONTROL_WR(bit);
  57. unsigned int timeout_cnt = 400; /* Takes max. 120us according to
  58. * datasheet.
  59. */
  60. writew(mask, ctrl_addr);
  61. while (timeout_cnt--) {
  62. if (!(readw(ctrl_addr) & mask))
  63. break;
  64. udelay(1);
  65. }
  66. return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
  67. }
  68. static u8 mxc_w1_read_byte(struct udevice *dev)
  69. {
  70. struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
  71. struct mxc_w1_regs *regs = pdata->regs;
  72. u16 status;
  73. if (dev_get_driver_data(dev) < 2) {
  74. int i;
  75. u8 ret = 0;
  76. for (i = 0; i < 8; i++)
  77. ret |= (mxc_w1_touch_bit(pdata, 1) << i);
  78. return ret;
  79. }
  80. readw(&regs->tx_rx);
  81. writew(0xFF, &regs->tx_rx);
  82. do {
  83. udelay(1); /* Without this bytes are sometimes duplicated... */
  84. status = readw(&regs->interrupt);
  85. } while (!(status & MXC_W1_INTERRUPT_RBF));
  86. return (u8)readw(&regs->tx_rx);
  87. }
  88. static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
  89. {
  90. struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
  91. struct mxc_w1_regs *regs = pdata->regs;
  92. u16 status;
  93. if (dev_get_driver_data(dev) < 2) {
  94. int i;
  95. for (i = 0; i < 8; i++)
  96. mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
  97. return;
  98. }
  99. readw(&regs->tx_rx);
  100. writew(byte, &regs->tx_rx);
  101. do {
  102. udelay(1);
  103. status = readw(&regs->interrupt);
  104. } while (!(status & MXC_W1_INTERRUPT_TSRE));
  105. }
  106. static bool mxc_w1_reset(struct udevice *dev)
  107. {
  108. struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
  109. u16 reg_val;
  110. writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
  111. do {
  112. reg_val = readw(&pdata->regs->control);
  113. } while (reg_val & MXC_W1_CONTROL_RPP);
  114. return !(reg_val & MXC_W1_CONTROL_PST);
  115. }
  116. static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
  117. {
  118. struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
  119. u8 id_bit = mxc_w1_touch_bit(pdata, 1);
  120. u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
  121. u8 retval;
  122. if (id_bit && comp_bit)
  123. return 0x03; /* error */
  124. if (!id_bit && !comp_bit) {
  125. /* Both bits are valid, take the direction given */
  126. retval = bdir ? 0x04 : 0;
  127. } else {
  128. /* Only one bit is valid, take that direction */
  129. bdir = id_bit;
  130. retval = id_bit ? 0x05 : 0x02;
  131. }
  132. mxc_w1_touch_bit(pdata, bdir);
  133. return retval;
  134. }
  135. static int mxc_w1_ofdata_to_platdata(struct udevice *dev)
  136. {
  137. struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
  138. fdt_addr_t addr;
  139. addr = dev_read_addr(dev);
  140. if (addr == FDT_ADDR_T_NONE)
  141. return -EINVAL;
  142. pdata->regs = (struct mxc_w1_regs *)addr;
  143. return 0;
  144. };
  145. static int mxc_w1_probe(struct udevice *dev)
  146. {
  147. struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
  148. unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
  149. unsigned int clkdiv;
  150. if (clkrate < 10000000) {
  151. dev_err(dev, "input clock frequency (%u Hz) too low\n",
  152. clkrate);
  153. return -EINVAL;
  154. }
  155. clkdiv = clkrate / 1000000;
  156. clkrate /= clkdiv;
  157. if (clkrate < 980000 || clkrate > 1020000) {
  158. dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
  159. return -EINVAL;
  160. }
  161. writew(clkdiv - 1, &pdata->regs->time_divider);
  162. return 0;
  163. }
  164. static const struct w1_ops mxc_w1_ops = {
  165. .read_byte = mxc_w1_read_byte,
  166. .reset = mxc_w1_reset,
  167. .triplet = mxc_w1_triplet,
  168. .write_byte = mxc_w1_write_byte,
  169. };
  170. static const struct udevice_id mxc_w1_id[] = {
  171. { .compatible = "fsl,imx21-owire", .data = 1 },
  172. { .compatible = "fsl,imx27-owire", .data = 1 },
  173. { .compatible = "fsl,imx31-owire", .data = 1 },
  174. { .compatible = "fsl,imx51-owire", .data = 1 },
  175. { .compatible = "fsl,imx25-owire", .data = 2 },
  176. { .compatible = "fsl,imx35-owire", .data = 2 },
  177. { .compatible = "fsl,imx50-owire", .data = 2 },
  178. { .compatible = "fsl,imx53-owire", .data = 2 },
  179. { },
  180. };
  181. U_BOOT_DRIVER(mxc_w1_drv) = {
  182. .id = UCLASS_W1,
  183. .name = "mxc_w1_drv",
  184. .of_match = mxc_w1_id,
  185. .ofdata_to_platdata = mxc_w1_ofdata_to_platdata,
  186. .ops = &mxc_w1_ops,
  187. .platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata),
  188. .probe = mxc_w1_probe,
  189. };