sor.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2011-2013, NVIDIA Corporation.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <panel.h>
  11. #include <syscon.h>
  12. #include <video_bridge.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch-tegra/dc.h>
  16. #include <linux/delay.h>
  17. #include "displayport.h"
  18. #include "sor.h"
  19. #include <linux/err.h>
  20. #define DEBUG_SOR 0
  21. #define APBDEV_PMC_DPD_SAMPLE 0x20
  22. #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE 0
  23. #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE 1
  24. #define APBDEV_PMC_SEL_DPD_TIM 0x1c8
  25. #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT 0x7f
  26. #define APBDEV_PMC_IO_DPD2_REQ 0x1c0
  27. #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT 25
  28. #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25)
  29. #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25)
  30. #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT 30
  31. #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30)
  32. #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30)
  33. #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30)
  34. #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30)
  35. #define APBDEV_PMC_IO_DPD2_STATUS 0x1c4
  36. #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT 25
  37. #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
  38. #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
  39. struct tegra_dc_sor_data {
  40. void *base;
  41. void *pmc_base;
  42. u8 portnum; /* 0 or 1 */
  43. int power_is_up;
  44. struct udevice *panel;
  45. };
  46. static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
  47. {
  48. return readl((u32 *)sor->base + reg);
  49. }
  50. static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
  51. u32 val)
  52. {
  53. writel(val, (u32 *)sor->base + reg);
  54. }
  55. static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
  56. u32 reg, u32 mask, u32 val)
  57. {
  58. u32 reg_val = tegra_sor_readl(sor, reg);
  59. reg_val &= ~mask;
  60. reg_val |= val;
  61. tegra_sor_writel(sor, reg, reg_val);
  62. }
  63. void tegra_dp_disable_tx_pu(struct udevice *dev)
  64. {
  65. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  66. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  67. DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE);
  68. }
  69. void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg,
  70. u32 vs_reg, u32 pc_reg, u8 pc_supported)
  71. {
  72. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  73. tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg);
  74. tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg);
  75. if (pc_supported) {
  76. tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask,
  77. pc_reg);
  78. }
  79. }
  80. static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
  81. u32 mask, u32 exp_val,
  82. int poll_interval_us, int timeout_ms)
  83. {
  84. u32 reg_val = 0;
  85. ulong start;
  86. start = get_timer(0);
  87. do {
  88. reg_val = tegra_sor_readl(sor, reg);
  89. if (((reg_val & mask) == exp_val))
  90. return 0;
  91. udelay(poll_interval_us);
  92. } while (get_timer(start) < timeout_ms);
  93. debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
  94. reg, reg_val, mask, exp_val);
  95. return -ETIMEDOUT;
  96. }
  97. int tegra_dc_sor_set_power_state(struct udevice *dev, int pu_pd)
  98. {
  99. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  100. u32 reg_val;
  101. u32 orig_val;
  102. orig_val = tegra_sor_readl(sor, PWR);
  103. reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
  104. PWR_NORMAL_STATE_PD; /* normal state only */
  105. if (reg_val == orig_val)
  106. return 0; /* No update needed */
  107. reg_val |= PWR_SETTING_NEW_TRIGGER;
  108. tegra_sor_writel(sor, PWR, reg_val);
  109. /* Poll to confirm it is done */
  110. if (tegra_dc_sor_poll_register(sor, PWR,
  111. PWR_SETTING_NEW_DEFAULT_MASK,
  112. PWR_SETTING_NEW_DONE,
  113. 100, TEGRA_SOR_TIMEOUT_MS)) {
  114. debug("dc timeout waiting for SOR_PWR = NEW_DONE\n");
  115. return -EFAULT;
  116. }
  117. return 0;
  118. }
  119. void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena,
  120. u8 training_pattern,
  121. const struct tegra_dp_link_config *link_cfg)
  122. {
  123. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  124. u32 reg_val;
  125. reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
  126. if (ena)
  127. reg_val |= DP_LINKCTL_ENABLE_YES;
  128. else
  129. reg_val &= DP_LINKCTL_ENABLE_NO;
  130. reg_val &= ~DP_LINKCTL_TUSIZE_MASK;
  131. reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);
  132. if (link_cfg->enhanced_framing)
  133. reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;
  134. tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
  135. switch (training_pattern) {
  136. case training_pattern_1:
  137. tegra_sor_writel(sor, DP_TPG, 0x41414141);
  138. break;
  139. case training_pattern_2:
  140. case training_pattern_3:
  141. reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
  142. 0x43434343 : 0x42424242;
  143. tegra_sor_writel(sor, DP_TPG, reg_val);
  144. break;
  145. default:
  146. tegra_sor_writel(sor, DP_TPG, 0x50505050);
  147. break;
  148. }
  149. }
  150. static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
  151. int pu, int is_lvds)
  152. {
  153. u32 reg_val;
  154. /* SOR lane sequencer */
  155. if (pu) {
  156. reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
  157. LANE_SEQ_CTL_SEQUENCE_DOWN |
  158. LANE_SEQ_CTL_NEW_POWER_STATE_PU;
  159. } else {
  160. reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
  161. LANE_SEQ_CTL_SEQUENCE_UP |
  162. LANE_SEQ_CTL_NEW_POWER_STATE_PD;
  163. }
  164. if (is_lvds)
  165. reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;
  166. else
  167. reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;
  168. tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);
  169. if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL,
  170. LANE_SEQ_CTL_SETTING_MASK,
  171. LANE_SEQ_CTL_SETTING_NEW_DONE,
  172. 100, TEGRA_SOR_TIMEOUT_MS)) {
  173. debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n");
  174. return -1;
  175. }
  176. return 0;
  177. }
  178. static int tegra_dc_sor_power_dplanes(struct udevice *dev,
  179. u32 lane_count, int pu)
  180. {
  181. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  182. u32 reg_val;
  183. reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
  184. if (pu) {
  185. switch (lane_count) {
  186. case 4:
  187. reg_val |= (DP_PADCTL_PD_TXD_3_NO |
  188. DP_PADCTL_PD_TXD_2_NO);
  189. /* fall through */
  190. case 2:
  191. reg_val |= DP_PADCTL_PD_TXD_1_NO;
  192. case 1:
  193. reg_val |= DP_PADCTL_PD_TXD_0_NO;
  194. break;
  195. default:
  196. debug("dp: invalid lane number %d\n", lane_count);
  197. return -1;
  198. }
  199. tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
  200. tegra_dc_sor_set_lane_count(dev, lane_count);
  201. }
  202. return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
  203. }
  204. void tegra_dc_sor_set_panel_power(struct udevice *dev, int power_up)
  205. {
  206. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  207. u32 reg_val;
  208. reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
  209. if (power_up)
  210. reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;
  211. else
  212. reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;
  213. tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
  214. }
  215. static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
  216. u32 pwm_dutycycle)
  217. {
  218. tegra_sor_writel(sor, PWM_DIV, pwm_div);
  219. tegra_sor_writel(sor, PWM_CTL,
  220. (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) |
  221. PWM_CTL_SETTING_NEW_TRIGGER);
  222. if (tegra_dc_sor_poll_register(sor, PWM_CTL,
  223. PWM_CTL_SETTING_NEW_SHIFT,
  224. PWM_CTL_SETTING_NEW_DONE,
  225. 100, TEGRA_SOR_TIMEOUT_MS)) {
  226. debug("dp: timeout while waiting for SOR PWM setting\n");
  227. }
  228. }
  229. static void tegra_dc_sor_set_dp_mode(struct udevice *dev,
  230. const struct tegra_dp_link_config *link_cfg)
  231. {
  232. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  233. u32 reg_val;
  234. tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
  235. tegra_dc_sor_set_dp_linkctl(dev, 1, training_pattern_none, link_cfg);
  236. reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
  237. reg_val &= ~DP_CONFIG_WATERMARK_MASK;
  238. reg_val |= link_cfg->watermark;
  239. reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;
  240. reg_val |= (link_cfg->active_count <<
  241. DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
  242. reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;
  243. reg_val |= (link_cfg->active_frac <<
  244. DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
  245. if (link_cfg->activepolarity)
  246. reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
  247. else
  248. reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
  249. reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
  250. DP_CONFIG_RD_RESET_VAL_NEGATIVE);
  251. tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);
  252. /* program h/vblank sym */
  253. tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS,
  254. DP_AUDIO_HBLANK_SYMBOLS_MASK,
  255. link_cfg->hblank_sym);
  256. tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS,
  257. DP_AUDIO_VBLANK_SYMBOLS_MASK,
  258. link_cfg->vblank_sym);
  259. }
  260. static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
  261. {
  262. tegra_sor_writel(sor, SUPER_STATE0, 0);
  263. tegra_sor_writel(sor, SUPER_STATE0, 1);
  264. tegra_sor_writel(sor, SUPER_STATE0, 0);
  265. }
  266. static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
  267. {
  268. tegra_sor_writel(sor, STATE0, 0);
  269. tegra_sor_writel(sor, STATE0, 1);
  270. tegra_sor_writel(sor, STATE0, 0);
  271. }
  272. static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
  273. {
  274. u32 reg_val;
  275. void *pmc_base = sor->pmc_base;
  276. if (up) {
  277. writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
  278. pmc_base + APBDEV_PMC_DPD_SAMPLE);
  279. writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
  280. }
  281. reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
  282. reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
  283. APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
  284. reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
  285. APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
  286. APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
  287. APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
  288. writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
  289. /* Polling */
  290. u32 temp = 10 * 1000;
  291. do {
  292. udelay(20);
  293. reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
  294. if (temp > 20)
  295. temp -= 20;
  296. else
  297. break;
  298. } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
  299. if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {
  300. debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
  301. return -EIO;
  302. }
  303. if (up) {
  304. writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
  305. pmc_base + APBDEV_PMC_DPD_SAMPLE);
  306. }
  307. return 0;
  308. }
  309. void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int)
  310. {
  311. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  312. u32 reg_val;
  313. reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
  314. if (is_int)
  315. reg_val |= DP_SPARE_PANEL_INTERNAL;
  316. else
  317. reg_val &= ~DP_SPARE_PANEL_INTERNAL;
  318. reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
  319. DP_SPARE_SEQ_ENABLE_YES;
  320. tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
  321. }
  322. void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw,
  323. u8 *lane_count)
  324. {
  325. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  326. u32 reg_val;
  327. reg_val = tegra_sor_readl(sor, CLK_CNTRL);
  328. *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)
  329. >> CLK_CNTRL_DP_LINK_SPEED_SHIFT;
  330. reg_val = tegra_sor_readl(sor,
  331. DP_LINKCTL(sor->portnum));
  332. switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {
  333. case DP_LINKCTL_LANECOUNT_ZERO:
  334. *lane_count = 0;
  335. break;
  336. case DP_LINKCTL_LANECOUNT_ONE:
  337. *lane_count = 1;
  338. break;
  339. case DP_LINKCTL_LANECOUNT_TWO:
  340. *lane_count = 2;
  341. break;
  342. case DP_LINKCTL_LANECOUNT_FOUR:
  343. *lane_count = 4;
  344. break;
  345. default:
  346. printf("Unknown lane count\n");
  347. }
  348. }
  349. void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw)
  350. {
  351. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  352. tegra_sor_write_field(sor, CLK_CNTRL,
  353. CLK_CNTRL_DP_LINK_SPEED_MASK,
  354. link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
  355. }
  356. void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count)
  357. {
  358. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  359. u32 reg_val;
  360. reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
  361. reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;
  362. switch (lane_count) {
  363. case 0:
  364. break;
  365. case 1:
  366. reg_val |= DP_LINKCTL_LANECOUNT_ONE;
  367. break;
  368. case 2:
  369. reg_val |= DP_LINKCTL_LANECOUNT_TWO;
  370. break;
  371. case 4:
  372. reg_val |= DP_LINKCTL_LANECOUNT_FOUR;
  373. break;
  374. default:
  375. /* 0 should be handled earlier. */
  376. printf("dp: Invalid lane count %d\n", lane_count);
  377. return;
  378. }
  379. tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
  380. }
  381. /*
  382. * The SOR power sequencer does not work for t124 so SW has to
  383. * go through the power sequence manually
  384. * Power up steps from spec:
  385. * STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL
  386. * 1 1 1 1 1 1 1 1
  387. * 2 1 1 1 1 1 0 1
  388. * 3 1 1 0 1 1 0 1
  389. * 4 1 0 0 0 0 0 1
  390. * 5 0 0 0 0 0 0 1
  391. */
  392. static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds)
  393. {
  394. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  395. u32 reg;
  396. int ret;
  397. if (sor->power_is_up)
  398. return 0;
  399. /*
  400. * If for some reason it is already powered up, don't do it again.
  401. * This can happen if U-Boot is the secondary boot loader.
  402. */
  403. reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
  404. if (reg & DP_PADCTL_PD_TXD_0_NO)
  405. return 0;
  406. /* Set link bw */
  407. tegra_dc_sor_set_link_bandwidth(dev, is_lvds ?
  408. CLK_CNTRL_DP_LINK_SPEED_LVDS :
  409. CLK_CNTRL_DP_LINK_SPEED_G1_62);
  410. /* step 1 */
  411. tegra_sor_write_field(sor, PLL2,
  412. PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
  413. PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
  414. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
  415. PLL2_AUX7_PORT_POWERDOWN_ENABLE |
  416. PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
  417. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
  418. tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
  419. PLL0_VCOPD_MASK, /* PLLVCOPD */
  420. PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
  421. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  422. DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
  423. DP_PADCTL_PAD_CAL_PD_POWERDOWN);
  424. /* step 2 */
  425. ret = tegra_dc_sor_io_set_dpd(sor, 1);
  426. if (ret)
  427. return ret;
  428. udelay(15);
  429. /* step 3 */
  430. tegra_sor_write_field(sor, PLL2,
  431. PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
  432. PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
  433. udelay(25);
  434. /* step 4 */
  435. tegra_sor_write_field(sor, PLL0,
  436. PLL0_PWR_MASK | /* PDPLL */
  437. PLL0_VCOPD_MASK, /* PLLVCOPD */
  438. PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
  439. /* PLLCAPD */
  440. tegra_sor_write_field(sor, PLL2,
  441. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
  442. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
  443. udelay(225);
  444. /* step 5 PDPORT */
  445. tegra_sor_write_field(sor, PLL2,
  446. PLL2_AUX7_PORT_POWERDOWN_MASK,
  447. PLL2_AUX7_PORT_POWERDOWN_DISABLE);
  448. sor->power_is_up = 1;
  449. return 0;
  450. }
  451. #if DEBUG_SOR
  452. static void dump_sor_reg(struct tegra_dc_sor_data *sor)
  453. {
  454. #define DUMP_REG(a) printk(BIOS_INFO, \
  455. "%-32s %03x %08x\n", \
  456. #a, a, tegra_sor_readl(sor, a));
  457. DUMP_REG(SUPER_STATE0);
  458. DUMP_REG(SUPER_STATE1);
  459. DUMP_REG(STATE0);
  460. DUMP_REG(STATE1);
  461. DUMP_REG(NV_HEAD_STATE0(0));
  462. DUMP_REG(NV_HEAD_STATE0(1));
  463. DUMP_REG(NV_HEAD_STATE1(0));
  464. DUMP_REG(NV_HEAD_STATE1(1));
  465. DUMP_REG(NV_HEAD_STATE2(0));
  466. DUMP_REG(NV_HEAD_STATE2(1));
  467. DUMP_REG(NV_HEAD_STATE3(0));
  468. DUMP_REG(NV_HEAD_STATE3(1));
  469. DUMP_REG(NV_HEAD_STATE4(0));
  470. DUMP_REG(NV_HEAD_STATE4(1));
  471. DUMP_REG(NV_HEAD_STATE5(0));
  472. DUMP_REG(NV_HEAD_STATE5(1));
  473. DUMP_REG(CRC_CNTRL);
  474. DUMP_REG(CLK_CNTRL);
  475. DUMP_REG(CAP);
  476. DUMP_REG(PWR);
  477. DUMP_REG(TEST);
  478. DUMP_REG(PLL0);
  479. DUMP_REG(PLL1);
  480. DUMP_REG(PLL2);
  481. DUMP_REG(PLL3);
  482. DUMP_REG(CSTM);
  483. DUMP_REG(LVDS);
  484. DUMP_REG(CRCA);
  485. DUMP_REG(CRCB);
  486. DUMP_REG(SEQ_CTL);
  487. DUMP_REG(LANE_SEQ_CTL);
  488. DUMP_REG(SEQ_INST(0));
  489. DUMP_REG(SEQ_INST(1));
  490. DUMP_REG(SEQ_INST(2));
  491. DUMP_REG(SEQ_INST(3));
  492. DUMP_REG(SEQ_INST(4));
  493. DUMP_REG(SEQ_INST(5));
  494. DUMP_REG(SEQ_INST(6));
  495. DUMP_REG(SEQ_INST(7));
  496. DUMP_REG(SEQ_INST(8));
  497. DUMP_REG(PWM_DIV);
  498. DUMP_REG(PWM_CTL);
  499. DUMP_REG(MSCHECK);
  500. DUMP_REG(XBAR_CTRL);
  501. DUMP_REG(DP_LINKCTL(0));
  502. DUMP_REG(DP_LINKCTL(1));
  503. DUMP_REG(DC(0));
  504. DUMP_REG(DC(1));
  505. DUMP_REG(LANE_DRIVE_CURRENT(0));
  506. DUMP_REG(PR(0));
  507. DUMP_REG(LANE4_PREEMPHASIS(0));
  508. DUMP_REG(POSTCURSOR(0));
  509. DUMP_REG(DP_CONFIG(0));
  510. DUMP_REG(DP_CONFIG(1));
  511. DUMP_REG(DP_MN(0));
  512. DUMP_REG(DP_MN(1));
  513. DUMP_REG(DP_PADCTL(0));
  514. DUMP_REG(DP_PADCTL(1));
  515. DUMP_REG(DP_DEBUG(0));
  516. DUMP_REG(DP_DEBUG(1));
  517. DUMP_REG(DP_SPARE(0));
  518. DUMP_REG(DP_SPARE(1));
  519. DUMP_REG(DP_TPG);
  520. return;
  521. }
  522. #endif
  523. static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
  524. int is_lvds,
  525. const struct tegra_dp_link_config *link_cfg,
  526. const struct display_timing *timing)
  527. {
  528. const int head_num = 0;
  529. u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num;
  530. u32 vtotal, htotal;
  531. u32 vsync_end, hsync_end;
  532. u32 vblank_end, hblank_end;
  533. u32 vblank_start, hblank_start;
  534. reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
  535. STATE1_ASY_PROTOCOL_DP_A;
  536. reg_val |= STATE1_ASY_SUBOWNER_NONE |
  537. STATE1_ASY_CRCMODE_COMPLETE_RASTER;
  538. reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
  539. reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
  540. reg_val |= (link_cfg->bits_per_pixel > 18) ?
  541. STATE1_ASY_PIXELDEPTH_BPP_24_444 :
  542. STATE1_ASY_PIXELDEPTH_BPP_18_444;
  543. tegra_sor_writel(sor, STATE1, reg_val);
  544. /*
  545. * Skipping programming NV_HEAD_STATE0, assuming:
  546. * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
  547. */
  548. vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
  549. timing->vactive.typ + timing->vfront_porch.typ;
  550. htotal = timing->hsync_len.typ + timing->hback_porch.typ +
  551. timing->hactive.typ + timing->hfront_porch.typ;
  552. tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
  553. vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
  554. htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
  555. vsync_end = timing->vsync_len.typ - 1;
  556. hsync_end = timing->hsync_len.typ - 1;
  557. tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
  558. vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
  559. hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
  560. vblank_end = vsync_end + timing->vback_porch.typ;
  561. hblank_end = hsync_end + timing->hback_porch.typ;
  562. tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
  563. vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
  564. hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
  565. vblank_start = vblank_end + timing->vactive.typ;
  566. hblank_start = hblank_end + timing->hactive.typ;
  567. tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
  568. vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
  569. hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
  570. /* TODO: adding interlace mode support */
  571. tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
  572. tegra_sor_write_field(sor, CSTM,
  573. CSTM_ROTCLK_DEFAULT_MASK |
  574. CSTM_LVDS_EN_ENABLE,
  575. 2 << CSTM_ROTCLK_SHIFT |
  576. is_lvds ? CSTM_LVDS_EN_ENABLE :
  577. CSTM_LVDS_EN_DISABLE);
  578. tegra_dc_sor_config_pwm(sor, 1024, 1024);
  579. }
  580. static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
  581. {
  582. u32 reg_val = readl(&disp_ctrl->cmd.state_access);
  583. writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
  584. writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
  585. /* Enable DC now - otherwise pure text console may not show. */
  586. writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
  587. &disp_ctrl->cmd.disp_cmd);
  588. writel(reg_val, &disp_ctrl->cmd.state_access);
  589. }
  590. int tegra_dc_sor_enable_dp(struct udevice *dev,
  591. const struct tegra_dp_link_config *link_cfg)
  592. {
  593. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  594. int ret;
  595. tegra_sor_write_field(sor, CLK_CNTRL,
  596. CLK_CNTRL_DP_CLK_SEL_MASK,
  597. CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
  598. tegra_sor_write_field(sor, PLL2,
  599. PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
  600. PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
  601. udelay(25);
  602. tegra_sor_write_field(sor, PLL3,
  603. PLL3_PLLVDD_MODE_MASK,
  604. PLL3_PLLVDD_MODE_V3_3);
  605. tegra_sor_writel(sor, PLL0,
  606. 0xf << PLL0_ICHPMP_SHFIT |
  607. 0x3 << PLL0_VCOCAP_SHIFT |
  608. PLL0_PLLREG_LEVEL_V45 |
  609. PLL0_RESISTORSEL_EXT |
  610. PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
  611. tegra_sor_write_field(sor, PLL2,
  612. PLL2_AUX1_SEQ_MASK |
  613. PLL2_AUX9_LVDSEN_OVERRIDE |
  614. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
  615. PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
  616. PLL2_AUX9_LVDSEN_OVERRIDE |
  617. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
  618. tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
  619. PLL1_TMDS_TERM_ENABLE);
  620. if (tegra_dc_sor_poll_register(sor, PLL2,
  621. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
  622. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
  623. 100, TEGRA_SOR_TIMEOUT_MS)) {
  624. printf("DP failed to lock PLL\n");
  625. return -EIO;
  626. }
  627. tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
  628. PLL2_AUX7_PORT_POWERDOWN_MASK,
  629. PLL2_AUX2_OVERRIDE_POWERDOWN |
  630. PLL2_AUX7_PORT_POWERDOWN_DISABLE);
  631. ret = tegra_dc_sor_power_up(dev, 0);
  632. if (ret) {
  633. debug("DP failed to power up\n");
  634. return ret;
  635. }
  636. /* re-enable SOR clock */
  637. clock_sor_enable_edp_clock();
  638. /* Power up lanes */
  639. tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1);
  640. tegra_dc_sor_set_dp_mode(dev, link_cfg);
  641. debug("%s ret\n", __func__);
  642. return 0;
  643. }
  644. int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
  645. const struct tegra_dp_link_config *link_cfg,
  646. const struct display_timing *timing)
  647. {
  648. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  649. struct dc_ctlr *disp_ctrl;
  650. u32 reg_val;
  651. /* Use the first display controller */
  652. debug("%s\n", __func__);
  653. disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
  654. tegra_dc_sor_enable_dc(disp_ctrl);
  655. tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
  656. writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
  657. writel(0x9f, &disp_ctrl->cmd.state_ctrl);
  658. writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
  659. PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
  660. &disp_ctrl->cmd.disp_pow_ctrl);
  661. reg_val = tegra_sor_readl(sor, TEST);
  662. if (reg_val & TEST_ATTACHED_TRUE)
  663. return -EEXIST;
  664. tegra_sor_writel(sor, SUPER_STATE1,
  665. SUPER_STATE1_ATTACHED_NO);
  666. /*
  667. * Enable display2sor clock at least 2 cycles before DC start,
  668. * to clear sor internal valid signal.
  669. */
  670. writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
  671. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  672. writel(0, &disp_ctrl->disp.disp_win_opt);
  673. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  674. /* Attach head */
  675. tegra_dc_sor_update(sor);
  676. tegra_sor_writel(sor, SUPER_STATE1,
  677. SUPER_STATE1_ATTACHED_YES);
  678. tegra_sor_writel(sor, SUPER_STATE1,
  679. SUPER_STATE1_ATTACHED_YES |
  680. SUPER_STATE1_ASY_HEAD_OP_AWAKE |
  681. SUPER_STATE1_ASY_ORMODE_NORMAL);
  682. tegra_dc_sor_super_update(sor);
  683. /* Enable dc */
  684. reg_val = readl(&disp_ctrl->cmd.state_access);
  685. writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
  686. writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
  687. &disp_ctrl->cmd.disp_cmd);
  688. writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
  689. writel(reg_val, &disp_ctrl->cmd.state_access);
  690. if (tegra_dc_sor_poll_register(sor, TEST,
  691. TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
  692. TEST_ACT_HEAD_OPMODE_AWAKE,
  693. 100,
  694. TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
  695. printf("dc timeout waiting for OPMOD = AWAKE\n");
  696. return -ETIMEDOUT;
  697. } else {
  698. debug("%s: sor is attached\n", __func__);
  699. }
  700. #if DEBUG_SOR
  701. dump_sor_reg(sor);
  702. #endif
  703. debug("%s: ret=%d\n", __func__, 0);
  704. return 0;
  705. }
  706. void tegra_dc_sor_set_lane_parm(struct udevice *dev,
  707. const struct tegra_dp_link_config *link_cfg)
  708. {
  709. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  710. tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
  711. link_cfg->drive_current);
  712. tegra_sor_writel(sor, PR(sor->portnum),
  713. link_cfg->preemphasis);
  714. tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
  715. link_cfg->postcursor);
  716. tegra_sor_writel(sor, LVDS, 0);
  717. tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
  718. tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count);
  719. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  720. DP_PADCTL_TX_PU_ENABLE |
  721. DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
  722. DP_PADCTL_TX_PU_ENABLE |
  723. 2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
  724. /* Precharge */
  725. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
  726. udelay(20);
  727. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
  728. }
  729. int tegra_dc_sor_set_voltage_swing(struct udevice *dev,
  730. const struct tegra_dp_link_config *link_cfg)
  731. {
  732. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  733. u32 drive_current = 0;
  734. u32 pre_emphasis = 0;
  735. /* Set to a known-good pre-calibrated setting */
  736. switch (link_cfg->link_bw) {
  737. case SOR_LINK_SPEED_G1_62:
  738. case SOR_LINK_SPEED_G2_7:
  739. drive_current = 0x13131313;
  740. pre_emphasis = 0;
  741. break;
  742. case SOR_LINK_SPEED_G5_4:
  743. debug("T124 does not support 5.4G link clock.\n");
  744. default:
  745. debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);
  746. return -ENOLINK;
  747. }
  748. tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current);
  749. tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);
  750. return 0;
  751. }
  752. void tegra_dc_sor_power_down_unused_lanes(struct udevice *dev,
  753. const struct tegra_dp_link_config *link_cfg)
  754. {
  755. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  756. u32 pad_ctrl = 0;
  757. int err = 0;
  758. switch (link_cfg->lane_count) {
  759. case 4:
  760. pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
  761. DP_PADCTL_PD_TXD_1_NO |
  762. DP_PADCTL_PD_TXD_2_NO |
  763. DP_PADCTL_PD_TXD_3_NO;
  764. break;
  765. case 2:
  766. pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
  767. DP_PADCTL_PD_TXD_1_NO |
  768. DP_PADCTL_PD_TXD_2_YES |
  769. DP_PADCTL_PD_TXD_3_YES;
  770. break;
  771. case 1:
  772. pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
  773. DP_PADCTL_PD_TXD_1_YES |
  774. DP_PADCTL_PD_TXD_2_YES |
  775. DP_PADCTL_PD_TXD_3_YES;
  776. break;
  777. default:
  778. printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
  779. return;
  780. }
  781. pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
  782. tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);
  783. err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
  784. if (err) {
  785. debug("Wait for lane power down failed: %d\n", err);
  786. return;
  787. }
  788. }
  789. int tegra_sor_precharge_lanes(struct udevice *dev,
  790. const struct tegra_dp_link_config *cfg)
  791. {
  792. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  793. u32 val = 0;
  794. switch (cfg->lane_count) {
  795. case 4:
  796. val |= (DP_PADCTL_PD_TXD_3_NO |
  797. DP_PADCTL_PD_TXD_2_NO);
  798. /* fall through */
  799. case 2:
  800. val |= DP_PADCTL_PD_TXD_1_NO;
  801. /* fall through */
  802. case 1:
  803. val |= DP_PADCTL_PD_TXD_0_NO;
  804. break;
  805. default:
  806. debug("dp: invalid lane number %d\n", cfg->lane_count);
  807. return -EINVAL;
  808. }
  809. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  810. (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
  811. (val << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
  812. udelay(100);
  813. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  814. (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
  815. 0);
  816. return 0;
  817. }
  818. static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable)
  819. {
  820. u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt);
  821. reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE;
  822. writel(reg_val, &disp_ctrl->disp.disp_win_opt);
  823. }
  824. int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
  825. {
  826. struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  827. int dc_reg_ctx[DC_REG_SAVE_SPACE];
  828. struct dc_ctlr *disp_ctrl;
  829. unsigned long dc_int_mask;
  830. int ret;
  831. debug("%s\n", __func__);
  832. /* Use the first display controller */
  833. disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
  834. /* Sleep mode */
  835. tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
  836. SUPER_STATE1_ASY_ORMODE_SAFE |
  837. SUPER_STATE1_ATTACHED_YES);
  838. tegra_dc_sor_super_update(sor);
  839. tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx);
  840. if (tegra_dc_sor_poll_register(sor, TEST,
  841. TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
  842. TEST_ACT_HEAD_OPMODE_SLEEP, 100,
  843. TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
  844. debug("dc timeout waiting for OPMOD = SLEEP\n");
  845. ret = -ETIMEDOUT;
  846. goto err;
  847. }
  848. tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
  849. SUPER_STATE1_ASY_ORMODE_SAFE |
  850. SUPER_STATE1_ATTACHED_NO);
  851. /* Mask DC interrupts during the 2 dummy frames required for detach */
  852. dc_int_mask = readl(&disp_ctrl->cmd.int_mask);
  853. writel(0, &disp_ctrl->cmd.int_mask);
  854. /* Stop DC->SOR path */
  855. tegra_dc_sor_enable_sor(disp_ctrl, false);
  856. ret = tegra_dc_sor_general_act(disp_ctrl);
  857. if (ret)
  858. goto err;
  859. /* Stop DC */
  860. writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);
  861. ret = tegra_dc_sor_general_act(disp_ctrl);
  862. if (ret)
  863. goto err;
  864. tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx);
  865. writel(dc_int_mask, &disp_ctrl->cmd.int_mask);
  866. return 0;
  867. err:
  868. debug("%s: ret=%d\n", __func__, ret);
  869. return ret;
  870. }
  871. static int tegra_sor_set_backlight(struct udevice *dev, int percent)
  872. {
  873. struct tegra_dc_sor_data *priv = dev_get_priv(dev);
  874. int ret;
  875. ret = panel_enable_backlight(priv->panel);
  876. if (ret) {
  877. debug("sor: Cannot enable panel backlight\n");
  878. return ret;
  879. }
  880. return 0;
  881. }
  882. static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
  883. {
  884. struct tegra_dc_sor_data *priv = dev_get_priv(dev);
  885. int ret;
  886. priv->base = (void *)dev_read_addr(dev);
  887. priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
  888. if (IS_ERR(priv->pmc_base))
  889. return PTR_ERR(priv->pmc_base);
  890. ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
  891. &priv->panel);
  892. if (ret) {
  893. debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
  894. dev->name, ret);
  895. return ret;
  896. }
  897. return 0;
  898. }
  899. static const struct video_bridge_ops tegra_sor_ops = {
  900. .set_backlight = tegra_sor_set_backlight,
  901. };
  902. static const struct udevice_id tegra_sor_ids[] = {
  903. { .compatible = "nvidia,tegra124-sor" },
  904. { }
  905. };
  906. U_BOOT_DRIVER(sor_tegra) = {
  907. .name = "sor_tegra",
  908. .id = UCLASS_VIDEO_BRIDGE,
  909. .of_match = tegra_sor_ids,
  910. .ofdata_to_platdata = tegra_sor_ofdata_to_platdata,
  911. .ops = &tegra_sor_ops,
  912. .priv_auto_alloc_size = sizeof(struct tegra_dc_sor_data),
  913. };