display.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Google Inc.
  4. *
  5. * Extracted from Chromium coreboot commit 3f59b13d
  6. */
  7. #include <common.h>
  8. #include <bootstage.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <errno.h>
  12. #include <display.h>
  13. #include <edid.h>
  14. #include <lcd.h>
  15. #include <log.h>
  16. #include <part.h>
  17. #include <video.h>
  18. #include <asm/gpio.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/pwm.h>
  22. #include <asm/arch-tegra/dc.h>
  23. #include <dm/uclass-internal.h>
  24. #include <linux/delay.h>
  25. #include "displayport.h"
  26. /* return in 1000ths of a Hertz */
  27. static int tegra_dc_calc_refresh(const struct display_timing *timing)
  28. {
  29. int h_total, v_total, refresh;
  30. int pclk = timing->pixelclock.typ;
  31. h_total = timing->hactive.typ + timing->hfront_porch.typ +
  32. timing->hback_porch.typ + timing->hsync_len.typ;
  33. v_total = timing->vactive.typ + timing->vfront_porch.typ +
  34. timing->vback_porch.typ + timing->vsync_len.typ;
  35. if (!pclk || !h_total || !v_total)
  36. return 0;
  37. refresh = pclk / h_total;
  38. refresh *= 1000;
  39. refresh /= v_total;
  40. return refresh;
  41. }
  42. static void print_mode(const struct display_timing *timing)
  43. {
  44. int refresh = tegra_dc_calc_refresh(timing);
  45. debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
  46. timing->hactive.typ, timing->vactive.typ, refresh / 1000,
  47. refresh % 1000, timing->pixelclock.typ);
  48. }
  49. static int update_display_mode(struct dc_ctlr *disp_ctrl,
  50. const struct display_timing *timing,
  51. int href_to_sync, int vref_to_sync)
  52. {
  53. print_mode(timing);
  54. writel(0x1, &disp_ctrl->disp.disp_timing_opt);
  55. writel(vref_to_sync << 16 | href_to_sync,
  56. &disp_ctrl->disp.ref_to_sync);
  57. writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
  58. &disp_ctrl->disp.sync_width);
  59. writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
  60. timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
  61. writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
  62. timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
  63. writel(timing->hactive.typ | (timing->vactive.typ << 16),
  64. &disp_ctrl->disp.disp_active);
  65. /**
  66. * We want to use PLLD_out0, which is PLLD / 2:
  67. * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
  68. *
  69. * Currently most panels work inside clock range 50MHz~100MHz, and PLLD
  70. * has some requirements to have VCO in range 500MHz~1000MHz (see
  71. * clock.c for more detail). To simplify calculation, we set
  72. * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
  73. * may be calculated by clock_display, to allow wider frequency range.
  74. *
  75. * Note ShiftClockDiv is a 7.1 format value.
  76. */
  77. const u32 shift_clock_div = 1;
  78. writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
  79. ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
  80. &disp_ctrl->disp.disp_clk_ctrl);
  81. debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
  82. timing->pixelclock.typ, shift_clock_div);
  83. return 0;
  84. }
  85. static u32 tegra_dc_poll_register(void *reg,
  86. u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
  87. {
  88. u32 temp = timeout_us;
  89. u32 reg_val = 0;
  90. do {
  91. udelay(poll_interval_us);
  92. reg_val = readl(reg);
  93. if (timeout_us > poll_interval_us)
  94. timeout_us -= poll_interval_us;
  95. else
  96. break;
  97. } while ((reg_val & mask) != exp_val);
  98. if ((reg_val & mask) == exp_val)
  99. return 0; /* success */
  100. return temp;
  101. }
  102. int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
  103. {
  104. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  105. if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
  106. GENERAL_ACT_REQ, 0, 100,
  107. DC_POLL_TIMEOUT_MS * 1000)) {
  108. debug("dc timeout waiting for DC to stop\n");
  109. return -ETIMEDOUT;
  110. }
  111. return 0;
  112. }
  113. static struct display_timing min_mode = {
  114. .hsync_len = { .typ = 1 },
  115. .vsync_len = { .typ = 1 },
  116. .hback_porch = { .typ = 20 },
  117. .vback_porch = { .typ = 0 },
  118. .hactive = { .typ = 16 },
  119. .vactive = { .typ = 16 },
  120. .hfront_porch = { .typ = 1 },
  121. .vfront_porch = { .typ = 2 },
  122. };
  123. /* Disable windows and set minimum raster timings */
  124. void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
  125. int *dc_reg_ctx)
  126. {
  127. const int href_to_sync = 0, vref_to_sync = 1;
  128. int selected_windows, i;
  129. selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
  130. /* Store and clear window options */
  131. for (i = 0; i < DC_N_WINDOWS; ++i) {
  132. writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
  133. dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
  134. writel(0, &disp_ctrl->win.win_opt);
  135. writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
  136. }
  137. writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
  138. /* Store current raster timings and set minimum timings */
  139. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
  140. writel(href_to_sync | (vref_to_sync << 16),
  141. &disp_ctrl->disp.ref_to_sync);
  142. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
  143. writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
  144. &disp_ctrl->disp.sync_width);
  145. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
  146. writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
  147. &disp_ctrl->disp.back_porch);
  148. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
  149. writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
  150. &disp_ctrl->disp.front_porch);
  151. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
  152. writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
  153. &disp_ctrl->disp.disp_active);
  154. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  155. }
  156. /* Restore previous windows status and raster timings */
  157. void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
  158. int *dc_reg_ctx)
  159. {
  160. int selected_windows, i;
  161. selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
  162. for (i = 0; i < DC_N_WINDOWS; ++i) {
  163. writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
  164. writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
  165. writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
  166. }
  167. writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
  168. writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
  169. writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
  170. writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
  171. writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
  172. writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
  173. writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
  174. }
  175. static int tegra_depth_for_bpp(int bpp)
  176. {
  177. switch (bpp) {
  178. case 32:
  179. return COLOR_DEPTH_R8G8B8A8;
  180. case 16:
  181. return COLOR_DEPTH_B5G6R5;
  182. default:
  183. debug("Unsupported LCD bit depth");
  184. return -1;
  185. }
  186. }
  187. static int update_window(struct dc_ctlr *disp_ctrl,
  188. u32 frame_buffer, int fb_bits_per_pixel,
  189. const struct display_timing *timing)
  190. {
  191. const u32 colour_white = 0xffffff;
  192. int colour_depth;
  193. u32 val;
  194. writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
  195. writel(((timing->vactive.typ << 16) | timing->hactive.typ),
  196. &disp_ctrl->win.size);
  197. writel(((timing->vactive.typ << 16) |
  198. (timing->hactive.typ * fb_bits_per_pixel / 8)),
  199. &disp_ctrl->win.prescaled_size);
  200. writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
  201. 32 * 32), &disp_ctrl->win.line_stride);
  202. colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
  203. if (colour_depth == -1)
  204. return -EINVAL;
  205. writel(colour_depth, &disp_ctrl->win.color_depth);
  206. writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
  207. writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
  208. &disp_ctrl->win.dda_increment);
  209. writel(colour_white, &disp_ctrl->disp.blend_background_color);
  210. writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
  211. &disp_ctrl->cmd.disp_cmd);
  212. writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
  213. val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  214. val |= GENERAL_UPDATE | WIN_A_UPDATE;
  215. writel(val, &disp_ctrl->cmd.state_ctrl);
  216. /* Enable win_a */
  217. val = readl(&disp_ctrl->win.win_opt);
  218. writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
  219. return 0;
  220. }
  221. static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
  222. {
  223. /* do not accept interrupts during initialization */
  224. writel(0x00000000, &disp_ctrl->cmd.int_mask);
  225. writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
  226. &disp_ctrl->cmd.state_access);
  227. writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
  228. writel(0x00000000, &disp_ctrl->win.win_opt);
  229. writel(0x00000000, &disp_ctrl->win.byte_swap);
  230. writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
  231. writel(0x00000000, &disp_ctrl->win.pos);
  232. writel(0x00000000, &disp_ctrl->win.h_initial_dda);
  233. writel(0x00000000, &disp_ctrl->win.v_initial_dda);
  234. writel(0x00000000, &disp_ctrl->win.dda_increment);
  235. writel(0x00000000, &disp_ctrl->win.dv_ctrl);
  236. writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
  237. writel(0x00000000, &disp_ctrl->win.blend_match_select);
  238. writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
  239. writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
  240. writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
  241. writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
  242. writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
  243. writel(0x00000000, &disp_ctrl->com.crc_checksum);
  244. writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
  245. writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
  246. writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
  247. writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
  248. writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
  249. return 0;
  250. }
  251. static void dump_config(int panel_bpp, struct display_timing *timing)
  252. {
  253. printf("timing->hactive.typ = %d\n", timing->hactive.typ);
  254. printf("timing->vactive.typ = %d\n", timing->vactive.typ);
  255. printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
  256. printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
  257. printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
  258. printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
  259. printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ);
  260. printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
  261. printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
  262. printf("panel_bits_per_pixel = %d\n", panel_bpp);
  263. }
  264. static int display_update_config_from_edid(struct udevice *dp_dev,
  265. int *panel_bppp,
  266. struct display_timing *timing)
  267. {
  268. return display_read_timing(dp_dev, timing);
  269. }
  270. static int display_init(struct udevice *dev, void *lcdbase,
  271. int fb_bits_per_pixel, struct display_timing *timing)
  272. {
  273. struct display_plat *disp_uc_plat;
  274. struct dc_ctlr *dc_ctlr;
  275. struct udevice *dp_dev;
  276. const int href_to_sync = 1, vref_to_sync = 1;
  277. int panel_bpp = 18; /* default 18 bits per pixel */
  278. u32 plld_rate;
  279. int ret;
  280. /*
  281. * Before we probe the display device (eDP), tell it that this device
  282. * is the source of the display data.
  283. */
  284. ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
  285. if (ret) {
  286. debug("%s: device '%s' display not found (ret=%d)\n", __func__,
  287. dev->name, ret);
  288. return ret;
  289. }
  290. disp_uc_plat = dev_get_uclass_platdata(dp_dev);
  291. debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
  292. disp_uc_plat);
  293. disp_uc_plat->src_dev = dev;
  294. ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
  295. if (ret) {
  296. debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
  297. return ret;
  298. }
  299. dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
  300. if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
  301. debug("%s: Failed to decode display timing\n", __func__);
  302. return -EINVAL;
  303. }
  304. ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
  305. if (ret) {
  306. debug("%s: Failed to decode EDID, using defaults\n", __func__);
  307. dump_config(panel_bpp, timing);
  308. }
  309. /*
  310. * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
  311. * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
  312. * update_display_mode() for detail.
  313. */
  314. plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
  315. if (plld_rate == 0) {
  316. printf("dc: clock init failed\n");
  317. return -EIO;
  318. } else if (plld_rate != timing->pixelclock.typ * 2) {
  319. debug("dc: plld rounded to %u\n", plld_rate);
  320. timing->pixelclock.typ = plld_rate / 2;
  321. }
  322. /* Init dc */
  323. ret = tegra_dc_init(dc_ctlr);
  324. if (ret) {
  325. debug("dc: init failed\n");
  326. return ret;
  327. }
  328. /* Configure dc mode */
  329. ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
  330. if (ret) {
  331. debug("dc: failed to configure display mode\n");
  332. return ret;
  333. }
  334. /* Enable dp */
  335. ret = display_enable(dp_dev, panel_bpp, timing);
  336. if (ret) {
  337. debug("dc: failed to enable display: ret=%d\n", ret);
  338. return ret;
  339. }
  340. ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
  341. if (ret) {
  342. debug("dc: failed to update window\n");
  343. return ret;
  344. }
  345. debug("%s: ready\n", __func__);
  346. return 0;
  347. }
  348. enum {
  349. /* Maximum LCD size we support */
  350. LCD_MAX_WIDTH = 1920,
  351. LCD_MAX_HEIGHT = 1200,
  352. LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
  353. };
  354. static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
  355. enum video_log2_bpp l2bpp)
  356. {
  357. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  358. struct display_timing timing;
  359. int ret;
  360. clock_set_up_plldp();
  361. clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
  362. clock_enable(PERIPH_ID_HOST1X);
  363. clock_enable(PERIPH_ID_DISP1);
  364. clock_enable(PERIPH_ID_PWM);
  365. clock_enable(PERIPH_ID_DPAUX);
  366. clock_enable(PERIPH_ID_SOR0);
  367. udelay(2);
  368. reset_set_enable(PERIPH_ID_HOST1X, 0);
  369. reset_set_enable(PERIPH_ID_DISP1, 0);
  370. reset_set_enable(PERIPH_ID_PWM, 0);
  371. reset_set_enable(PERIPH_ID_DPAUX, 0);
  372. reset_set_enable(PERIPH_ID_SOR0, 0);
  373. ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
  374. if (ret)
  375. return ret;
  376. uc_priv->xsize = roundup(timing.hactive.typ, 16);
  377. uc_priv->ysize = timing.vactive.typ;
  378. uc_priv->bpix = l2bpp;
  379. video_set_flush_dcache(dev, 1);
  380. debug("%s: done\n", __func__);
  381. return 0;
  382. }
  383. static int tegra124_lcd_probe(struct udevice *dev)
  384. {
  385. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  386. ulong start;
  387. int ret;
  388. start = get_timer(0);
  389. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd");
  390. ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
  391. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  392. debug("LCD init took %lu ms\n", get_timer(start));
  393. if (ret)
  394. printf("%s: Error %d\n", __func__, ret);
  395. return 0;
  396. }
  397. static int tegra124_lcd_bind(struct udevice *dev)
  398. {
  399. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  400. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  401. (1 << VIDEO_BPP16) / 8;
  402. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  403. return 0;
  404. }
  405. static const struct udevice_id tegra124_lcd_ids[] = {
  406. { .compatible = "nvidia,tegra124-dc" },
  407. { }
  408. };
  409. U_BOOT_DRIVER(tegra124_dc) = {
  410. .name = "tegra124-dc",
  411. .id = UCLASS_VIDEO,
  412. .of_match = tegra124_lcd_ids,
  413. .bind = tegra124_lcd_bind,
  414. .probe = tegra124_lcd_probe,
  415. };